verilog to MyHDL conversion

Hello All,

I am trying to convert exiting verilog code to MyHDL.

This is in hopes of getting a person interested in MyHDL.

See the verilog file and my attempt to convert at

https://gist.github.com/95d06caf184fc1976d65.git

Are verilog && in myhdl written as & this?  I was getting 

errors when using &&.

The code that starts with BSCAN_SPARTAN6, I believe came 

from a template.  I was hoping on user jtag.verilog_code = \

to include it, in my the generated verilog file.  When I move 

line 72 """ to line 74 of jtagser.py I get the quoted text but not the 

other instance that I am trying to convert.


This line in verilog o_rx_data <= { ck_tdi, o_rx_data[7:1] }; converted 

o_rx_data <= ck_tdio_rx_data[7-1:1]; did I write this python 

correctly?

Thanks in advance.

All help is appreciated. Edward Vidal Jr. e-mail [email protected] 915-595-1613

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