Re: Dual port ram, mixed width byte enables.

Christopher Felton <[email protected]> Tue, 19 Apr 2016 07:46:10 -0500
Newsgroups gmane.comp.python.myhdl
Message-ID <CAECZzK8bDbMEezAcWgdNwAAib4f1K_--hQbtb7LvG0Jm39Jtjw@mail.gmail.com>
On Tue, Apr 19, 2016 at 7:32 AM, Samuele Disegna <[email protected]> wrote:

> Yes! There is a multidimensional array that enables indexing of the
> smaller port (or the ability to have byte enables).
>

Yes that will be a problem :(

There are a couple options: first, try and rework the example without
the multidimension array.  Second, you could use the user defined
code and wrap the template.  That would probably be the fastest and
you would be able to still model the same logic in myhdl just not
convert the multidim array.

Regards,
Chris

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