Re: Dual port ram, mixed width byte enables.
Josy Boelen <[email protected]> Tue, 19 Apr 2016 16:16:01 +0000 (UTC)
| Newsgroups | gmane.comp.python.myhdl |
|---|---|
| Message-ID | <[email protected]> |
Christopher Felton <chris.felton <at> gmail.com> writes: > > > Josy, > I am not 100% sure that it is limited to only multidim, I haven'tresearched this but I thought you could build mix port by using a model of the BRAM prims (1bit width) and build them from the simple model. More of an elaboration / generate approach. > > If that doesn't work than the user code [1] would be the quickest > alternative (as we both stated). > > I think the Array will take some discussion etc. before it worked > in to the base. It is a fairly important feature and I am sure there > will be significant feedback from the core devs. It needs a clean > MEP etc. for discussion and review. I don't think it is something > that can be used in the near-term. > > Regards,Chris > > [1] http://docs.myhdl.org/en/stable/manual/conversion.html#user- defined-code Hi Chris, I am (painfully) aware that the 'Array' needs a lot of care - unfortunately I have little free time lately. I'll try better. Regards, Josy ------------------------------------------------------------------------------ Find and fix application performance issues faster with Applications Manager Applications Manager provides deep performance insights into multiple tiers of your business applications. It resolves application problems quickly and reduces your MTTR. Get your free trial! https://ad.doubleclick.net/ddm/clk/302982198;130105516;z _______________________________________________ myhdl-list mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/myhdl-list