Re: [EXT] Re: Inconsistency between simulation and conversion

This makes me wonder, in simulation is it actually incrementing counter.next, or is it incrementing the value of counter?

It doesn’t feel like having augmented operators work the way most people would expect (counter.next +=1 -> counter.next = counter + 1) is going to cause anyone any actual problem. Am I missing something? Or is it just harder to make work correctly than it’s worth?

Dave

From: Samuele Disegna [mailto:[email protected]]
Sent: Thursday, April 28, 2016 7:13 AM
To: General discussions on MyHDL
Subject: [EXT] Re: [myhdl-list] Inconsistency between simulation and conversion

On Thu, Apr 28, 2016 at 1:47 PM, Henry Gomersall <[email protected]<mailto:[email protected]>> wrote:
On 28/04/16 07:54, Nicolas Pinault wrote:
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
>
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
>

Incrementing .next is a slightly odd thing to want to do,

I would remove slightly to the sentence :).
You are supposed to do "counter.next = counter+1" and not "counter.next = counter.next+1"

Simulation in MyHDL is just execution of your code and you are allowed to do nasty things!

Samuele
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