Re: Inconsistency between simulation and conversion

Ok, "counter.next +=1" is not equivalent to "counter.next = counter+1".
Is it really true that most people expect that equivalence?

.next  is a python property that gives to you the intbv object
counter._next. That object will be incremented.
This makes sense to me.

Anyway while checking MyHDL sources I spotted a little bug:

at line 546
https://github.com/jandecaluwe/myhdl/blob/master/myhdl/_Signal.py
"def _augm(self)" should be  "_augm(self,arg)"
# augmented assignment not supported
def _augm(self):
raise TypeError("Signal object doesn't support augmented assignment")
__iadd__ = __isub__ = __imul__ = __ipow__ = __imod__ = _augm
__ior__ = __iand__ = __ixor__ = __irshift__ = __ilshift__ = _augm
__itruediv__ = __ifloordiv__ = _augm

On Thu, Apr 28, 2016 at 3:05 PM, Nicolas Pinault <[email protected]> wrote:

> Le 28/04/2016 à 13:47, Henry Gomersall a écrit :
>
> On 28/04/16 07:54, Nicolas Pinault wrote:
>
> When using this statement "counter.next += 1" I get an error when
> converting my design to VHDL :
>
> myhdl.ConversionError: in file
> Z:\myHDL_Tests\NoiseFilter\src\noise_filter.py, line 51:
>     Not supported: Augmented signal assignment
>
> This makes sense.
> However, this same statement does not trig any error when simulating the
> design.
> Is this the intended behaviour ?
>
>
> Incrementing .next is a slightly odd thing to want to do, but is
> possible given .next is likely an int type. Clearly it doesn't really
> make sense from the perspective of conversion.
>
> To be consistent, I expect simulation to raise an exception as conversion
> does.
>
> Nicolas
>
>
>
> Henry
>
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