Re: myhdl & co-simulation

On Sun, May 1, 2016 at 12:53 PM, Edward Vidal <[email protected]>
wrote:

> <snip>
>
> Should I create both a myhdl instance and instance in file
> tb_wbdeppsimple.v?
>

It depends on what you want to do.  If you want to create
the testbench in MyHDL then you want to connect the
MyHDL simulation to the Verilog simulation (Cosimulation).
If you want to do Verilog simulation only, you can do as you
have done and include the converted MyHDL blocks into
the Verilog.

Hope that helps,
Chris

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