Variable has same name as a hierarchical Signal

Hello All,

Trying to convert the follow Verilog to MyHDL

The Signals creating  the are the following
reg x_write_n,r_write_n;

    always @(posedge i_clk)
    begin
        { x_dstb_n, x_astb_n, x_write_n, x_depp }
            <= { i_dstb_n, i_astb_n, i_write_n, i_depp };
        { r_dstb_n, r_astb_n, r_write_n, r_depp }
            <= { x_dstb_n, x_astb_n, x_write_n, x_depp };
        { l_dstb_n, l_astb_n } <= { r_dstb_n, r_astb_n };
    end

    This is what I am doing.
    @always(i_clk.posedge)
    def rtl():
        x_dstb_n.next = i_dstb_n
        x_astb_n.next = i_astb_n
        x_write_n.next = i_write_n
        x_depp.next = i_depp
       
    @always(i_clk.posedge)
    def rtl1():        
        r_dstb_n.next = x_dstb_n
        r_astb_n.next = x_astb_n
        #r_write_n = x_write_n
        r_depp.next = x_depp
      
    @always(i_clk.posedge)
    def rtl2():        
        l_dstb_n.next = r_dstb_n
        l_astb_n.next = r_astb_n
        
The above code is adding 1 & 2 bit delays.
 In the simulation is see 1 clk delay between 
i_dstb_n & x_dstb_ni_astb_n & x_astb_ni_write_n & x_write_ni_depp & x_depp
In the simulation is see 2 clk delay between 
i_dstb_n & r_dstb_n
In the simulation is see 3 clk delay betweeni_dstb_n & l_dstb_n    
The toVerilog goes okay with line  #r_write_n = x_write_n commented out.

Uncommenting the line gets the follow error.
        
  File "/usr/local/lib/python2.7/dist-packages/myhdl-1.0dev-py2.7.egg/myhdl/conversion/_misc.py", line 149, in raiseError
    raise ConversionError(kind, msg, info)
myhdl.ConversionError: in file my_wbdepp.py, line 104:
    Variable has same name as a hierarchical Signal 

How do I convert these statements from Verilog to MyHDL.
I recall reading the initial values was currently disabled.    
    initial    x_dstb_n = 1'b1;
    initial    r_dstb_n = 1'b1;
    initial    l_dstb_n = 1'b1;
    initial    x_astb_n = 1'b1;
    initial    r_astb_n = 1'b1;
    initial    l_astb_n = 1'b1;
    
Any and all help is appreciated.
Thanks in advance. Edward Vidal Jr. e-mail [email protected] 915-595-1613

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