Re: Promoting RISC-V to a Tier 3 supported platform

Ross Barnowski via NumPy-Discussion <[email protected]> Tue, 12 May 2026 09:42:12 -0700
Newsgroups gmane.comp.python.numeric.general
Message-ID <CADyYXuoQQ3Xz_Sj+-h6qpxCCsCBW-UScz1bsV0vN8L72U4ZDbQ@mail.gmail.com>
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+1 from me!

On Tue, May 12, 2026 at 7:35=E2=80=AFAM Charles R Harris via NumPy-Discussi=
on <
[email protected]> wrote:

>
>
> On Tue, May 12, 2026 at 7:23=E2=80=AFAM Ralf Gommers via NumPy-Discussion=
 <
> [email protected]> wrote:
>
>> Hi all,
>>
>> There has been sustained interest in, and responsive contributors for,
>> RISC-V support in NumPy. There are now self-hosted runners from the RISE
>> project (https://riseproject.dev/), which we're about to get green (I
>> hope) on https://github.com/numpy/numpy/pull/30995.
>>
>> Their interest extends to adding RISC-V as a supported platform for whic=
h
>> we ship wheels on PyPI - see https://github.com/numpy/numpy/issues/30216=
.
>> It seems a little too early to consider crossing that bridge today, but
>> it's an up-and-coming platform so it's fairly likely that we'll consider=
 it
>> in the future I'd think.
>>
>> For now, I propose we add RISC-V as a Tier 3 platform at
>> https://numpy.org/neps/nep-0057-numpy-platform-support.html#tier-3, next
>> to ppc64le and Pyodide. That means we have CI support and contributors w=
ho
>> have stuck up their hand and can be pinged in case of platform-specific
>> issues that need addressing.
>>
>> We also have SIMD and CPU detection code specific to RISC-V, so having
>> native runners in CI will be quite helpful either way. And hopefully we =
can
>> disable the slow QEMU-based job once we're happy with the self-hosted
>> runners.
>>
>> Thoughts or concerns?
>>
>>
> +1.
>
> Chuck
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> Member address: [email protected]
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<div dir=3D"ltr">+1 from me!</div><br><div class=3D"gmail_quote gmail_quote=
_container"><div dir=3D"ltr" class=3D"gmail_attr">On Tue, May 12, 2026 at 7=
:35=E2=80=AFAM Charles R Harris via NumPy-Discussion &lt;<a href=3D"mailto:=
[email protected]">[email protected]</a>&gt; wrote:<br>=
</div><blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;b=
order-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir=3D"ltr"><d=
iv dir=3D"ltr"><br></div><br><div class=3D"gmail_quote"><div dir=3D"ltr" cl=
ass=3D"gmail_attr">On Tue, May 12, 2026 at 7:23=E2=80=AFAM Ralf Gommers via=
 NumPy-Discussion &lt;<a href=3D"mailto:[email protected]" target=
=3D"_blank">[email protected]</a>&gt; wrote:<br></div><blockquote=
 class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-left:1px so=
lid rgb(204,204,204);padding-left:1ex"><div dir=3D"ltr"><div>Hi all,</div><=
div><br></div><div>There has been sustained interest in, and responsive con=
tributors for, RISC-V support in NumPy. There are now self-hosted runners f=
rom the RISE project (<a href=3D"https://riseproject.dev/" target=3D"_blank=
">https://riseproject.dev/</a>), which we&#39;re about to get green (I hope=
) on=C2=A0<a href=3D"https://github.com/numpy/numpy/pull/30995" target=3D"_=
blank">https://github.com/numpy/numpy/pull/30995</a>.</div><div><br></div><=
div>Their interest extends to adding RISC-V as a supported platform for whi=
ch we ship wheels on PyPI - see <a href=3D"https://github.com/numpy/numpy/i=
ssues/30216" target=3D"_blank">https://github.com/numpy/numpy/issues/30216<=
/a>. It seems a little too early to consider crossing that bridge today, bu=
t it&#39;s an up-and-coming platform so it&#39;s fairly likely that we&#39;=
ll consider it in the future I&#39;d think.</div><div><br></div><div>For no=
w, I propose we add RISC-V as a Tier 3 platform at=C2=A0<a href=3D"https://=
numpy.org/neps/nep-0057-numpy-platform-support.html#tier-3" target=3D"_blan=
k">https://numpy.org/neps/nep-0057-numpy-platform-support.html#tier-3</a>, =
next to ppc64le and Pyodide. That means we have CI support and contributors=
 who have stuck up their hand and can be pinged in case of platform-specifi=
c issues that need addressing.=C2=A0</div><div><br></div><div>We also have =
SIMD and CPU detection code specific to RISC-V, so having native runners in=
 CI will be quite helpful either way. And hopefully we can disable the slow=
 QEMU-based job once we&#39;re happy with the self-hosted runners.</div><di=
v><br></div><div>Thoughts or concerns?</div><div><br></div></div></blockquo=
te><div><br></div><div>+1.</div><div><br></div><div>Chuck=C2=A0</div></div>=
</div>
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</blockquote></div>

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