Re: OpenEEG Questions

Greg Feneis <[email protected]> Thu, 24 Sep 2020 16:17:14 -0700
Newsgroups gmane.comp.science.openeeg.general
Message-ID <CAJdmZ-WJDoMQFDfcqe-LuP9JeZc1zKU6=3HiLcv8hgE865wJHw@mail.gmail.com>
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Hi Jordan,

Try this link to modify your subscription

https://lists.sourceforge.net/lists/listinfo/openeeg-list

Kind regards, Greg Feneis
(Pixel 3)


On Thu, Sep 24, 2020, 13:15 Jordan <[email protected]> wrote:

> Can you remove me from your mailing list?
>
> *Jordan Harris, Ph.D, LPC, LMFT*
>
> Trauma Therapist and Couples Counselor
>
> https://medium.com/@informedsimplicity
>
> Cell: (410) 300 3461
>
>
>
>
>
> On Wed, Sep 23, 2020 at 2:43 PM Yonah Elorza <[email protected]> wrote:
>
>> Hello all,
>>
>> Thank you all so much for your great advice. I'm starting prototyping
>> with one channel for now, to test my schematics and ICs, as well as my
>> control mechanisms. If I make any headway with my changes, I'll make sur=
e
>> to reach out to you all and give you an update!
>>
>> On Mon, Sep 21, 2020 at 5:44 AM Blago Gmail <[email protected]> wrote=
:
>>
>>> Hello  Yonah,
>>>
>>> Your idea for developing upgraded hardware for OpenEEG is definitely
>>> good!
>>>
>>> I wonder how many users feel "performance constrained" with current
>>> version?
>>>
>>> Here are you points:
>>>  >>> -Designing better noise cancelling to reduce commons noise,
>>>  >>> as well as noise between electrodes.
>>> You can gain significant improvements over signal to noise ratio if you
>>> "integrate" the signal processing chain down to the ADC - the so called
>>> Analog Front-End (AFE). What I mean under integration is to choose from
>>> available options multi-channel AFE implemented as integrated circuit
>>> (ASIC) - Texas-instruments, Analog-devices, Linear.... Those AFE chips
>>> are coming with TIA (first amplification, in Damian's terms) and PGA
>>> (second amplification) amplifiers + different type (single-ended or
>>> differential) and resolution, ADC inside. All of them requires some kin=
d
>>> of external digital control + reading out converted data samples (they
>>> don't memory buffers or storage place inside)
>>>
>>>  >>> -Integrating an FPGA into the design which acts as a
>>>  >>>    hardware Fast Fourier Transform
>>> I think you are underestimating the FPGAs. Despite the good use for
>>> signal processing, FPGA are good for implementing timing engines (the
>>> control signals needs to drive properly your AFE circuit).
>>>
>>> Imagine you are picking up an FPGA such as ZYNQ, who comes with dual
>>> core ARM processor inside... you are pretty much done with the
>>> configurable hardware you want. The firmware whiten for the ATMega
>>> should be ported to ARM but this will come with reward to have much mor=
e
>>> powerful processing unit. The FPGA fabric can be used for signal
>>> processing and controlling the external AFE. As you will end-up with
>>> good amount of data samples, better consider USB3/USB2 as interface wit=
h
>>> the PC.
>>>
>>>  >>>   -Making the circuit modular enough that you can stack
>>>  >>>    multiple together to have 4, 8, 16, etc. electrodes reading
>>>  >>>    at the same time.
>>> If you go the FPGA way, you will have ability to have reconfiguration o=
n
>>> PCB and IC levels.
>>>
>>>
>>>  >>>   -Long term: modifying the design of the circuit to work
>>>  >>>   without the AT processor, instead having hardware control
>>>  >>>   from the GPIO of a Raspberry Pi, and all data being fed raw
>>>  >>>    to either the GPIO or USB interface of the Pi.
>>> Raspberry Pi is good platform but OpenEEG is too hardware specific that
>>> I am afraid that platforms as Raspberry Pi or Begalbone or Arduino are
>>> too generic for this project.
>>>
>>> Kind regards,
>>>
>>> Blagomir Donchev
>>>
>>>
>>>
>>>
>>>
>>> On 20/09/2020 23:46, Dami=C3=A1n Filo wrote:
>>> > I am not, really... :D
>>> > Can you please define "leads"? Do you mean channels?
>>> > And what challenges?
>>> >
>>> > OpenEEG is in default built as bipolar EEG. That means for each
>>> channel
>>> > you need to connect two electrodes. The output is difference of
>>> voltage
>>> > between those two electrodes. But even with two electrodes you won't
>>> > need to make two amplfication circuits. The difference of voltages is
>>> > processed in the instrumentation amplifier (first amplifier) and then
>>> > the one difference signal is amplified further, so it can be reliably
>>> > converted to digital data. So you will need an amplification circuit
>>> > (cascade) for each channel (2 electrodes).
>>> > OpenEEG with v2 protocol and baud rate 115200 can support up to 6
>>> > channels, although ATmega16 can support 8. If there is need for more
>>> > channels, you would have to rewrite the firmware and change the baud
>>> > rate. But with that you would lose compatibility with software
>>> > supporting OpenEEG (like BrainBay).
>>> > I simply chose not to face those challenges and I stuck to the
>>> > specifications concerning OpenEEG compatibility. I use olimex v2
>>> > protocol firmware with ATmega16L.
>>> >
>>> >
>>> >
>>> > On Sun, Sep 20, 2020, 23:18 Steve Sterling <[email protected]
>>> > <mailto:[email protected]>> wrote:
>>> >
>>> >     You're really knowledgable about this Damian!  How do you work
>>> >     around the challenges with multiple leads, will each lead require
>>> >     it's own circuit?
>>> >
>>> >     Thanks,
>>> >     Steve
>>> >
>>> >     On Sun, Sep 20, 2020, 1:17 PM Dami=C3=A1n Filo <[email protected]=
m
>>> >     <mailto:[email protected]>> wrote:
>>> >
>>> >         I am sorry for the spam, but in my previous e-mail I said: "a=
ny
>>> >         of those changes you proposed are possible" - that is false.
>>> One
>>> >         change you mentioned was to feed raw data onto GPIO pins of
>>> RPi.
>>> >         That will not work, because what you need to do with the sign=
al
>>> >         is to convert it from analog to digital data through ADC and
>>> RPi
>>> >         doesn't have an ADCs. You can avoid using ATmega
>>> >         microcontrollers, but you still would have to use some extern=
al
>>> >         chip with ADC functions. And then you would have to program
>>> your
>>> >         own firmware and protocol, so you can use the data in
>>> >         applications running on RPi.
>>> >         Though what you can do with RPi is to feed the data directly
>>> >         from ATmega through native UART interface on RPi without the
>>> >         need for USB-UART chip. But about that, I am not really sure
>>> >         about the signalling voltage mismatch 5V/3.3V. So it is still
>>> >         preferred to use a USB interface with UART bridge like CP2102=
.
>>> >
>>> >         S pozdravom,
>>> >         Dami=C3=A1n Filo
>>> >
>>> >
>>> >         so 5. 9. 2020 o 21:49 Yonah Elorza <[email protected]
>>> >         <mailto:[email protected]>> nap=C3=ADsal(a):
>>> >
>>> >             Hello!
>>> >
>>> >             I'm a computer engineer interested in making some
>>> >             modifications to the OpenEEG circuit, and had a few
>>> >             questions, if anyone is available to answer them. I've re=
ad
>>> >             through all the documentation on the website, and have
>>> >             worked with the OpenEEG platform for a few years now, and
>>> >             wanted to see if the following was possible:
>>> >
>>> >             -Designing better noise cancelling to reduce commons nois=
e,
>>> >             as well as noise between electrodes.
>>> >             -Integrating an FPGA into the design which acts as a
>>> >             hardware Fast Fourier Transform
>>> >             -Making the circuit modular enough that you can stack
>>> >             multiple together to have 4, 8, 16, etc. electrodes readi=
ng
>>> >             at the same time.
>>> >             -Long term: modifying the design of the circuit to work
>>> >             without the AT processor, instead having hardware control
>>> >             from the GPIO of a Raspberry Pi, and all data being fed r=
aw
>>> >             to either the GPIO or USB interface of the Pi.
>>> >
>>> >             If anyone has reasons this wouldn't be possible, or if yo=
u
>>> >             have suggestions for any of these changes, please let me
>>> >             know. I absolutely love this project, and would love to b=
e
>>> >             able to contribute my own work to it.
>>> >
>>> >             --
>>> >             Best Regards,
>>> >             Yonah Elorza
>>> >             Columbia School of Engineering | Class of 2018
>>> >             Computer Engineering
>>> >             Tel: ( <tel:%28786%29%20205%20-%204304>305)-542-1735
>>> >             _______________________________________________
>>> >             Openeeg-list mailing list
>>> >             [email protected]
>>> >             <mailto:[email protected]>
>>> >             https://lists.sourceforge.net/lists/listinfo/openeeg-list
>>> >             Go to the above address to change your
>>> >             subscription options, e.g unsubscribe.
>>> >
>>> >         _______________________________________________
>>> >         Openeeg-list mailing list
>>> >         [email protected]
>>> >         <mailto:[email protected]>
>>> >         https://lists.sourceforge.net/lists/listinfo/openeeg-list
>>> >         Go to the above address to change your
>>> >         subscription options, e.g unsubscribe.
>>> >
>>> >     _______________________________________________
>>> >     Openeeg-list mailing list
>>> >     [email protected]
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>>> >     https://lists.sourceforge.net/lists/listinfo/openeeg-list
>>> >     Go to the above address to change your
>>> >     subscription options, e.g unsubscribe.
>>> >
>>> >
>>> >
>>> > _______________________________________________
>>> > Openeeg-list mailing list
>>> > [email protected]
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>>> > Go to the above address to change your
>>> > subscription options, e.g unsubscribe.
>>> >
>>>
>>>
>>> _______________________________________________
>>> Openeeg-list mailing list
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>>> https://lists.sourceforge.net/lists/listinfo/openeeg-list
>>> Go to the above address to change your
>>> subscription options, e.g unsubscribe.
>>>
>>
>>
>> --
>> Best Regards,
>> Yonah Elorza
>> Columbia School of Engineering | Class of 2018
>> Computer Engineering
>> Tel: ( <%28786%29%20205%20-%204304>305)-542-1735
>> _______________________________________________
>> Openeeg-list mailing list
>> [email protected]
>> https://lists.sourceforge.net/lists/listinfo/openeeg-list
>> Go to the above address to change your
>> subscription options, e.g unsubscribe.
>>
> _______________________________________________
> Openeeg-list mailing list
> [email protected]
> https://lists.sourceforge.net/lists/listinfo/openeeg-list
> Go to the above address to change your
> subscription options, e.g unsubscribe.
>

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<div dir=3D"auto">Hi Jordan,<div dir=3D"auto"><br></div><div dir=3D"auto">T=
ry this link to modify your subscription</div><div dir=3D"auto"><br></div><=
div dir=3D"auto"><a href=3D"https://lists.sourceforge.net/lists/listinfo/op=
eneeg-list">https://lists.sourceforge.net/lists/listinfo/openeeg-list</a><b=
r><br><div data-smartmail=3D"gmail_signature" dir=3D"auto">Kind regards, Gr=
eg Feneis<br>(Pixel 3)<br>=C2=A0=C2=A0=C2=A0 </div></div></div><br><div cla=
ss=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Thu, Sep 24, 20=
20, 13:15 Jordan &lt;<a href=3D"mailto:[email protected]">jocrharris@gma=
il.com</a>&gt; wrote:<br></div><blockquote class=3D"gmail_quote" style=3D"m=
argin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><div dir=3D"l=
tr"><div class=3D"gmail_default" style=3D"font-family:georgia,serif;font-si=
ze:large">Can you remove me from=C2=A0your mailing list?</div><div><div dir=
=3D"ltr" data-smartmail=3D"gmail_signature"><div dir=3D"ltr"><div><div dir=
=3D"ltr"><div dir=3D"ltr"><div dir=3D"ltr"><div dir=3D"ltr"><div dir=3D"ltr=
"><div dir=3D"ltr"><div dir=3D"ltr"><p style=3D"margin:0in 0in 0.0001pt"><f=
ont face=3D"verdana, sans-serif" size=3D"4"><b>Jordan Harris, Ph.D, LPC, LM=
FT</b><u></u></font></p><p style=3D"margin:0in 0in 0.0001pt"><font face=3D"=
verdana, sans-serif" size=3D"4">Trauma Therapist and Couples Counselor<u></=
u></font></p><p style=3D"margin:0in 0in 0.0001pt"><font face=3D"verdana, sa=
ns-serif" size=3D"4"><a href=3D"https://medium.com/@informedsimplicity" tar=
get=3D"_blank" rel=3D"noreferrer">https://medium.com/@informedsimplicity</a=
><br></font></p><p style=3D"margin:0in 0in 0.0001pt"><span style=3D"font-fa=
mily:verdana,sans-serif"><font size=3D"4">Cell: (410) 300 3461</font></span=
><br></p><p style=3D"margin:0in 0in 0.0001pt;font-size:11pt"><br><br></p></=
div></div></div></div></div></div></div></div></div></div></div><br></div><=
br><div class=3D"gmail_quote"><div dir=3D"ltr" class=3D"gmail_attr">On Wed,=
 Sep 23, 2020 at 2:43 PM Yonah Elorza &lt;<a href=3D"mailto:[email protected]=
om" target=3D"_blank" rel=3D"noreferrer">[email protected]</a>&gt; wrote:<b=
r></div><blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex=
;border-left:1px solid rgb(204,204,204);padding-left:1ex"><div dir=3D"ltr">=
Hello all,=C2=A0<div><br></div><div>Thank you all so much for your great ad=
vice. I&#39;m starting prototyping with one channel for now, to test my sch=
ematics and ICs, as well as my control mechanisms. If I make any headway wi=
th my changes, I&#39;ll make sure to reach out to you all and give you an u=
pdate!=C2=A0</div></div><br><div class=3D"gmail_quote"><div dir=3D"ltr" cla=
ss=3D"gmail_attr">On Mon, Sep 21, 2020 at 5:44 AM Blago Gmail &lt;<a href=
=3D"mailto:[email protected]" target=3D"_blank" rel=3D"noreferrer">don75=
[email protected]</a>&gt; wrote:<br></div><blockquote class=3D"gmail_quote" s=
tyle=3D"margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);pad=
ding-left:1ex">Hello=C2=A0 Yonah,<br>
<br>
Your idea for developing upgraded hardware for OpenEEG is definitely good!<=
br>
<br>
I wonder how many users feel &quot;performance constrained&quot; with curre=
nt version?<br>
<br>
Here are you points:<br>
=C2=A0&gt;&gt;&gt; -Designing better noise cancelling to reduce commons noi=
se,<br>
=C2=A0&gt;&gt;&gt; as well as noise between electrodes.<br>
You can gain significant improvements over signal to noise ratio if you <br=
>
&quot;integrate&quot; the signal processing chain down to the ADC - the so =
called <br>
Analog Front-End (AFE). What I mean under integration is to choose from <br=
>
available options multi-channel AFE implemented as integrated circuit <br>
(ASIC) - Texas-instruments, Analog-devices, Linear.... Those AFE chips <br>
are coming with TIA (first amplification, in Damian&#39;s terms) and PGA <b=
r>
(second amplification) amplifiers + different type (single-ended or <br>
differential) and resolution, ADC inside. All of them requires some kind <b=
r>
of external digital control + reading out converted data samples (they <br>
don&#39;t memory buffers or storage place inside)<br>
<br>
=C2=A0&gt;&gt;&gt; -Integrating an FPGA into the design which acts as a<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0 hardware Fast Fourier Transform<br>
I think you are underestimating the FPGAs. Despite the good use for <br>
signal processing, FPGA are good for implementing timing engines (the <br>
control signals needs to drive properly your AFE circuit).<br>
<br>
Imagine you are picking up an FPGA such as ZYNQ, who comes with dual <br>
core ARM processor inside... you are pretty much done with the <br>
configurable hardware you want. The firmware whiten for the ATMega <br>
should be ported to ARM but this will come with reward to have much more <b=
r>
powerful processing unit. The FPGA fabric can be used for signal <br>
processing and controlling the external AFE. As you will end-up with <br>
good amount of data samples, better consider USB3/USB2 as interface with <b=
r>
the PC.<br>
<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0-Making the circuit modular enough that you =
can stack<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0 multiple together to have 4, 8, 16, etc. el=
ectrodes reading<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0 at the same time.<br>
If you go the FPGA way, you will have ability to have reconfiguration on <b=
r>
PCB and IC levels.<br>
<br>
<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0-Long term: modifying the design of the circ=
uit to work<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0without the AT processor, instead having har=
dware control<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0from the GPIO of a Raspberry Pi, and all dat=
a being fed raw<br>
=C2=A0&gt;&gt;&gt;=C2=A0 =C2=A0 to either the GPIO or USB interface of the =
Pi.<br>
Raspberry Pi is good platform but OpenEEG is too hardware specific that <br=
>
I am afraid that platforms as Raspberry Pi or Begalbone or Arduino are <br>
too generic for this project.<br>
<br>
Kind regards,<br>
<br>
Blagomir Donchev<br>
<br>
<br>
<br>
<br>
<br>
On 20/09/2020 23:46, Dami=C3=A1n Filo wrote:<br>
&gt; I am not, really... :D<br>
&gt; Can you please define &quot;leads&quot;? Do you mean channels?<br>
&gt; And what challenges?<br>
&gt; <br>
&gt; OpenEEG is in default built as bipolar EEG. That means for each channe=
l <br>
&gt; you need to connect two electrodes. The output is difference of voltag=
e <br>
&gt; between those two electrodes. But even with two electrodes you won&#39=
;t <br>
&gt; need to make two amplfication circuits. The difference of voltages is =
<br>
&gt; processed in the instrumentation amplifier (first amplifier) and then =
<br>
&gt; the one difference signal is amplified further, so it can be reliably =
<br>
&gt; converted to digital data. So you will need an amplification circuit <=
br>
&gt; (cascade) for each channel (2 electrodes).<br>
&gt; OpenEEG with v2 protocol and baud rate 115200 can support up to 6 <br>
&gt; channels, although ATmega16 can support 8. If there is need for more <=
br>
&gt; channels, you would have to rewrite the firmware and change the baud <=
br>
&gt; rate. But with that you would lose compatibility with software <br>
&gt; supporting OpenEEG (like BrainBay).<br>
&gt; I simply chose not to face those challenges and I stuck to the <br>
&gt; specifications concerning OpenEEG compatibility. I use olimex v2 <br>
&gt; protocol firmware with ATmega16L.<br>
&gt; <br>
&gt; <br>
&gt; <br>
&gt; On Sun, Sep 20, 2020, 23:18 Steve Sterling &lt;<a href=3D"mailto:acust=
[email protected]" target=3D"_blank" rel=3D"noreferrer">[email protected]</a> =
<br>
&gt; &lt;mailto:<a href=3D"mailto:[email protected]" target=3D"_blank" rel=
=3D"noreferrer">[email protected]</a>&gt;&gt; wrote:<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0You&#39;re really knowledgable about this Damian!=
=C2=A0 How do you work<br>
&gt;=C2=A0 =C2=A0 =C2=A0around the challenges with multiple leads, will eac=
h lead require<br>
&gt;=C2=A0 =C2=A0 =C2=A0it&#39;s own circuit?<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0Thanks,<br>
&gt;=C2=A0 =C2=A0 =C2=A0Steve<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0On Sun, Sep 20, 2020, 1:17 PM Dami=C3=A1n Filo &lt;=
<a href=3D"mailto:[email protected]" target=3D"_blank" rel=3D"noreferrer">=
[email protected]</a><br>
&gt;=C2=A0 =C2=A0 =C2=A0&lt;mailto:<a href=3D"mailto:[email protected]" ta=
rget=3D"_blank" rel=3D"noreferrer">[email protected]</a>&gt;&gt; wrote:<br=
>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0I am sorry for the spam, but in my pr=
evious e-mail I said: &quot;any<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0of those changes you proposed are pos=
sible&quot; - that is false. One<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0change you mentioned was to feed raw =
data onto GPIO pins of RPi.<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0That will not work, because what you =
need to do with the signal<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0is to convert it from analog to digit=
al data through ADC and RPi<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0doesn&#39;t have an ADCs. You can avo=
id using ATmega<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0microcontrollers, but you still would=
 have to use some external<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0chip with ADC functions. And then you=
 would have to program your<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0own firmware and protocol, so you can=
 use the data in<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0applications running on RPi.<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Though what you can do with RPi is to=
 feed the data directly<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0from ATmega through native UART inter=
face on RPi without the<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0need for USB-UART chip. But about tha=
t, I am not really sure<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0about the signalling voltage mismatch=
 5V/3.3V. So it is still<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0preferred to use a USB interface with=
 UART bridge like CP2102.<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0S pozdravom,<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Dami=C3=A1n Filo<br>
&gt; <br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0so 5. 9. 2020 o=C2=A021:49 Yonah Elor=
za &lt;<a href=3D"mailto:[email protected]" target=3D"_blank" rel=3D"norefe=
rrer">[email protected]</a><br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&lt;mailto:<a href=3D"mailto:yonahel@=
gmail.com" target=3D"_blank" rel=3D"noreferrer">[email protected]</a>&gt;&g=
t; nap=C3=ADsal(a):<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Hello!<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0I&#39;m a computer engi=
neer interested in making some<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0modifications to the Op=
enEEG circuit, and had a few<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0questions, if anyone is=
 available to answer them. I&#39;ve read<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0through all the documen=
tation on the website, and have<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0worked with the OpenEEG=
 platform for a few years now, and<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0wanted to see if the fo=
llowing was possible:<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-Designing better noise=
 cancelling to reduce commons noise,<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0as well as noise betwee=
n electrodes.<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-Integrating an FPGA in=
to the design which acts as a<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0hardware Fast Fourier T=
ransform<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-Making the circuit mod=
ular enough that you can stack<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0multiple together to ha=
ve 4, 8, 16, etc. electrodes reading<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0at the same time.<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-Long term: modifying t=
he design of the circuit to work<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0without the AT processo=
r, instead having hardware control<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0from the GPIO of a Rasp=
berry Pi, and all data being fed raw<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0to either the GPIO or U=
SB interface of the Pi.<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0If anyone has reasons t=
his wouldn&#39;t be possible, or if you<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0have suggestions for an=
y of these changes, please let me<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0know. I absolutely love=
 this project, and would love to be<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0able to contribute my o=
wn work to it.<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0-- <br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Best Regards,<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Yonah Elorza<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Columbia School of Engi=
neering | Class of 2018<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Computer Engineering<br=
>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0Tel: ( &lt;tel:%28786%2=
9%20205%20-%204304&gt;305)-542-1735<br>
&gt;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0_______________________=
________________________<br>
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rceforge.net" target=3D"_blank" rel=3D"noreferrer">[email protected]=
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</blockquote></div><br clear=3D"all"><div><br></div>-- <br><div dir=3D"ltr"=
><div dir=3D"ltr"><div><div dir=3D"ltr"><div dir=3D"ltr" style=3D"font-size=
:12.8px"><div>Best Regards,<br></div>Yonah Elorza<br></div><div dir=3D"ltr"=
 style=3D"font-size:12.8px"><div style=3D"font-size:12.8px">Columbia School=
 of Engineering | Class of 2018</div><div style=3D"font-size:12.8px">Comput=
er Engineering</div><div style=3D"font-size:12.8px">Tel:=C2=A0<a href=3D"te=
l:%28786%29%20205%20-%204304" value=3D"+17862054304" style=3D"color:rgb(17,=
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