arm: handle unaligned addresses in Cortex-M cache ops

commit adb5e2e44f900bf419cd211d92bbe55f41c52f9c
Author: Aidan MacDonald <[email protected]>
Date:   Mon Jan 12 23:03:06 2026 +0000

    arm: handle unaligned addresses in Cortex-M cache ops
    
    For commit-type operations it's useful to be able to pass
    unaligned addresses, so round the address/size to ensure
    all cache lines in the address range are hit.
    
    Change-Id: Ibb23050ecf11b6ef6ab1dd517990a68ef62ecfa9

diff --git a/firmware/target/arm/cpucache-armv7m.c b/firmware/target/arm/cpucache-armv7m.c
index 5b9e084a1a..43f7ef8fe8 100644
--- a/firmware/target/arm/cpucache-armv7m.c
+++ b/firmware/target/arm/cpucache-armv7m.c
@@ -19,6 +19,7 @@
  *
  ****************************************************************************/
 #include "cpucache-armv7m.h"
+#include "system.h"
 #include "regs/cortex-m/cm_cache.h"
 
 /*
@@ -56,8 +57,9 @@ static inline void range_dcache_op(const void *base, unsigned int size,
 {
     arm_dsb();
 
-    uint32_t addr = (uint32_t)base;
-    uint32_t endaddr = addr + size;
+    uint32_t base_addr = (uint32_t)base;
+    uint32_t addr = CACHEALIGN_DOWN(base_addr);
+    uint32_t endaddr = CACHEALIGN_UP(base_addr + size);
 
     while (addr < endaddr)
     {
-- 
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