firmware: refactor CACHEALIGN_BITS/SIZE defines

commit 7eeb4e430243ebba89a33f6a39623230811959f1
Author: Aidan MacDonald <[email protected]>
Date:   Thu Feb 5 15:17:15 2026 +0000

    firmware: refactor CACHEALIGN_BITS/SIZE defines
    
    Mostly motivated by PP needing CACHEALIGN_SIZE in linker
    scripts, which can't include system.h, so move these to
    cpu.h instead. Also gets rid of the default 32 byte line
    size that was used if the target didn't define alignment
    itself. RK24xx, DM320, and JZ4740 were missing this but
    have been confirmed (from datasheets) to use 32-byte cache
    lines.
    
    Add checks to make sure the macros are appropriately
    (un)defined based on the HAVE_CPU_CACHE_ALIGN define,
    and make sure their values are consistent when they
    are defined.
    
    Disable HAVE_CPU_CACHE_ALIGN for hosted targets since it
    arguably doesn't matter if there's a cache, if we aren't
    responsible for cache maintenance.
    
    A few files in rbcodec use CACHEALIGN_SIZE, but these
    can be converted to MEM_ALIGN_SIZE, which is identical
    to CACHEALIGN_SIZE if the latter is defined. On other
    targets, it aligns to at least sizeof(intptr_t).
    
    Change-Id: If8cf8f6ec327dc3732f4cd5022a858546b9e63d6

diff --git a/apps/codecs.c b/apps/codecs.c
index e943191563..7bd2de367e 100644
--- a/apps/codecs.c
+++ b/apps/codecs.c
@@ -159,7 +159,7 @@ void codec_get_full_path(char *path, const char *codec_root_fn)
             CODEC_EXTENSION, codec_root_fn);
 }
 
-/* Returns pointer to and size of free codec RAM. Aligns to CACHEALIGN_SIZE. */
+/* Returns pointer to and size of free codec RAM. Aligns to MEM_ALIGN_SIZE. */
 void *codec_get_buffer_callback(size_t *size)
 {
     void *buf = &codecbuf[codec_size];
@@ -169,7 +169,7 @@ void *codec_get_buffer_callback(size_t *size)
         return NULL;
 
     *size = s;
-    ALIGN_BUFFER(buf, *size, CACHEALIGN_SIZE);
+    ALIGN_BUFFER(buf, *size, MEM_ALIGN_SIZE);
 
     return buf;
 }
diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds
index c91fa53b02..67ebe449e4 100644
--- a/apps/plugins/plugin.lds
+++ b/apps/plugins/plugin.lds
@@ -21,7 +21,6 @@ OUTPUT_FORMAT(elf32-littlemips)
 #else
 #define NOCACHE_BASE 	0x28000000
 #endif /* CPU_* */
-#define CACHEALIGN_SIZE 16
 #endif /* CPU_PP */
 
 #if CONFIG_CPU==IMX31L
diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h
index 0d3923ce75..0d4b02844d 100644
--- a/firmware/export/as3525.h
+++ b/firmware/export/as3525.h
@@ -21,6 +21,7 @@
 #define __AS3525_H__
 
 #define CACHEALIGN_BITS (5)
+#define CACHEALIGN_SIZE (32)
 
 #define UART_CHANNELS 1
 
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index e9e01e76cf..f064a96c72 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -25,60 +25,60 @@
 
 #if CONFIG_CPU == MCF5249
 #include "mcf5249.h"
-#endif
-#if CONFIG_CPU == MCF5250
+#elif CONFIG_CPU == MCF5250
 #include "mcf5250.h"
-#endif
-#if (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022)
+#elif (CONFIG_CPU == PP5020) || (CONFIG_CPU == PP5022)
 #include "pp5020.h"
-#endif
-#if CONFIG_CPU == PP5002
+#elif CONFIG_CPU == PP5002
 #include "pp5002.h"
-#endif
-#if CONFIG_CPU == PP5024
+#elif CONFIG_CPU == PP5024
 #include "pp5024.h"
-#endif
-#if CONFIG_CPU == PP6100
+#elif CONFIG_CPU == PP6100
 #include "pp6100.h"
-#endif
-#if CONFIG_CPU == S3C2440
+#elif CONFIG_CPU == S3C2440
 #include "s3c2440.h"
-#endif
-#if CONFIG_CPU == DM320
+#elif CONFIG_CPU == DM320
 #include "dm320.h"
-#endif
-#if CONFIG_CPU == IMX31L
+#elif CONFIG_CPU == IMX31L
 #include "imx31l.h"
-#endif
-#ifdef CPU_TCC780X
+#elif defined(CPU_TCC780X)
 #include "tcc780x.h"
-#endif
-#ifdef CPU_S5L87XX
+#elif defined(CPU_S5L87XX)
 #include "s5l87xx.h"
-#endif
-#if CONFIG_CPU == JZ4732
+#elif CONFIG_CPU == JZ4732
 #include "jz4740.h"
-#endif
-#if CONFIG_CPU == JZ4760B
+#elif CONFIG_CPU == JZ4760B
 #include "jz4760b.h"
-#endif
-#if CONFIG_CPU == AS3525
+#elif CONFIG_CPU == AS3525
 #include "as3525.h"
-#endif
-#if CONFIG_CPU == AS3525v2
+#elif CONFIG_CPU == AS3525v2
 #include "as3525v2.h"
-#endif
-#if CONFIG_CPU == IMX233
+#elif CONFIG_CPU == IMX233
 #include "imx233.h"
-#endif
-#if CONFIG_CPU == RK27XX
+#elif CONFIG_CPU == RK27XX
 #include "rk27xx.h"
-#endif
-#if CONFIG_CPU == X1000
+#elif CONFIG_CPU == X1000
 #include "x1000.h"
-#endif
-#if CONFIG_CPU == STM32H743
+#elif CONFIG_CPU == STM32H743
 #include "stm32h743.h"
 #endif
 
+#if (CONFIG_PLATFORM & PLATFORM_NATIVE) && (defined(CPU_ARM) || defined(CPU_MIPS))
+# define HAVE_CPU_CACHE_ALIGN
+#endif
+
+#if defined(HAVE_CPU_CACHE_ALIGN)
+# if !defined(CACHEALIGN_BITS)
+#  error "CPU header must define CACHEALIGN_BITS"
+# elif !defined(CACHEALIGN_SIZE)
+#  error "CPU header must define CACHEALIGN_SIZE"
+# elif CACHEALIGN_SIZE != (1u << CACHEALIGN_BITS)
+#  error "CACHEALIGN_SIZE and CACHEALIGN_BITS are inconsistent"
+# endif
+#else
+# if defined(CACHEALIGN_BITS) && defined(CACHEALIGN_SIZE)
+#  error "CACHEALIGN_BITS and CACHEALIGN_SIZE must not be defined for targets with no CPU cache"
+# endif
+#endif
+
 #endif /* __CPU_H */
diff --git a/firmware/export/dm320.h b/firmware/export/dm320.h
index bd6ca15407..6679c40790 100644
--- a/firmware/export/dm320.h
+++ b/firmware/export/dm320.h
@@ -36,6 +36,10 @@ extern unsigned long _lcdbuf2;
 extern unsigned long _ttbstart;
 #endif
 
+/* See https://www.heyrick.co.uk/blog/files/datasheets/tms320dm320part1.pdf */
+#define CACHEALIGN_BITS  5
+#define CACHEALIGN_SIZE  32
+
 #define TTB_BASE_ADDR    (_ttbstart) /* End of memory */
 #define FRAME            ((short *) (&_lcdbuf))  /* Right after TTB */
 #ifdef MROBE_500
diff --git a/firmware/export/jz4740.h b/firmware/export/jz4740.h
index c963aac852..b317ca59c3 100644
--- a/firmware/export/jz4740.h
+++ b/firmware/export/jz4740.h
@@ -40,6 +40,9 @@
 #ifndef __JZ4740_H__
 #define __JZ4740_H__
 
+#define CACHEALIGN_BITS (5)
+#define CACHEALIGN_SIZE (32)
+
 #ifndef __ASSEMBLER__
 
 #define REG8(addr)     (*(volatile unsigned char  *)(addr))
diff --git a/firmware/export/jz4760b.h b/firmware/export/jz4760b.h
index d56ffe69cd..c17939937e 100644
--- a/firmware/export/jz4760b.h
+++ b/firmware/export/jz4760b.h
@@ -37,6 +37,9 @@
 #ifndef __JZ4760B_H__
 #define __JZ4760B_H__
 
+#define CACHEALIGN_BITS (5)
+#define CACHEALIGN_SIZE (32)
+
 #if defined(__ASSEMBLER__)
         #ifndef __MIPS_ASSEMBLER
                 #define __MIPS_ASSEMBLER
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
index 5966f10d08..62a65a3d2e 100644
--- a/firmware/export/pp5002.h
+++ b/firmware/export/pp5002.h
@@ -23,7 +23,8 @@
 
 /* Much info gleaned and/or copied from the iPodLinux project. */
 
-#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+#define CACHEALIGN_BITS (4)  /* 2^4 = 16 bytes */
+#define CACHEALIGN_SIZE (16)
 
 #define DRAM_START       0x28000000
 
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index cd7cc80d66..c15d50ee38 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -23,7 +23,8 @@
 
 /* All info gleaned and/or copied from the iPodLinux project. */
 
-#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+#define CACHEALIGN_BITS (4)  /* 2^4 = 16 bytes */
+#define CACHEALIGN_SIZE (16)
 
 /* PCM addresses for obtaining buffers will be what DMA is using (physical) */
 #define HAVE_PCM_DMA_ADDRESS
diff --git a/firmware/export/rk27xx.h b/firmware/export/rk27xx.h
index dc6bca7cbd..8ab94add82 100644
--- a/firmware/export/rk27xx.h
+++ b/firmware/export/rk27xx.h
@@ -1,3 +1,7 @@
+/* See https://rockchip.fr/Rockchip%20RK27xx%20TRM%20V1.1.pdf */
+#define CACHEALIGN_BITS 5
+#define CACHEALIGN_SIZE 32
+
 /* ARM part only for now */
 #define AHB_SRAM 0x00000000
 
diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h
index d2de6d25c8..c0dc97aed5 100644
--- a/firmware/export/s3c2440.h
+++ b/firmware/export/s3c2440.h
@@ -22,6 +22,7 @@
 #define __S3C2440_H__
 
 #define CACHEALIGN_BITS (5)
+#define CACHEALIGN_SIZE (32)
 
 #define LCD_BUFFER_SIZE (320*240*2)
 #define TTB_SIZE (0x4000)
diff --git a/firmware/export/s5l87xx.h b/firmware/export/s5l87xx.h
index ee43d60ced..bb3aab16ba 100644
--- a/firmware/export/s5l87xx.h
+++ b/firmware/export/s5l87xx.h
@@ -31,9 +31,11 @@
 #define VOID_PTR_PTR_T       void* volatile*
 
 #if CONFIG_CPU==S5L8700 || CONFIG_CPU==S5L8701
-#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
+#define CACHEALIGN_BITS (4)  /* 2^4 = 16 bytes */
+#define CACHEALIGN_SIZE (16)
 #elif CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
-#define CACHEALIGN_BITS (5) /* 2^5 = 32 bytes */
+#define CACHEALIGN_BITS (5)  /* 2^5 = 32 bytes */
+#define CACHEALIGN_SIZE (32)
 #endif
 
 #if CONFIG_CPU==S5L8702 || CONFIG_CPU==S5L8720
diff --git a/firmware/export/stm32h743.h b/firmware/export/stm32h743.h
index add2130f5f..89643e3132 100644
--- a/firmware/export/stm32h743.h
+++ b/firmware/export/stm32h743.h
@@ -25,6 +25,7 @@
 
 #define CACHE_SIZE              (16 * 1024)
 #define CACHEALIGN_BITS         5
+#define CACHEALIGN_SIZE         32
 
 #define DCACHE_SIZE             CACHE_SIZE
 #define DCACHE_WAYS             0x4
diff --git a/firmware/export/system.h b/firmware/export/system.h
index edbeb5763c..fd8f7cae01 100644
--- a/firmware/export/system.h
+++ b/firmware/export/system.h
@@ -258,17 +258,6 @@ static inline void cpu_boost_unlock(void)
 #define DISABLE_INTERRUPTS  HIGHEST_IRQ_LEVEL
 #endif
 
-/* Define this, if the CPU may take advantage of cache aligment. Is enabled
- * for all ARM CPUs. */
-#ifdef CPU_ARM
-    #define HAVE_CPU_CACHE_ALIGN
-    #define MIN_STACK_ALIGN 8
-#endif
-
-#ifdef CPU_MIPS
-    #define HAVE_CPU_CACHE_ALIGN
-#endif
-
 /* Define this if target has support for generating backtraces */
 #if defined(CPU_ARM) || \
     (defined(CPU_MIPS) && (CONFIG_PLATFORM & PLATFORM_NATIVE))
@@ -277,22 +266,13 @@ static inline void cpu_boost_unlock(void)
 #endif
 #endif
 
-#ifndef MIN_STACK_ALIGN
-#define MIN_STACK_ALIGN (sizeof (uintptr_t))
+/* ARM ABIs generally require 8-byte stack alignment */
+#ifdef CPU_ARM
+    #define MIN_STACK_ALIGN 8
 #endif
 
-/* Calculate CACHEALIGN_SIZE from CACHEALIGN_BITS */
-#ifdef CACHEALIGN_SIZE
-    /* undefine, if defined. always calculate from CACHEALIGN_BITS */
-    #undef CACHEALIGN_SIZE
-#endif
-#ifdef CACHEALIGN_BITS
-    /* CACHEALIGN_SIZE = 2 ^ CACHEALIGN_BITS */
-    #define CACHEALIGN_SIZE (1u << CACHEALIGN_BITS)
-#else
-    /* FIXME: set to maximum known cache alignment of supported CPUs */
-    #define CACHEALIGN_BITS  5
-    #define CACHEALIGN_SIZE 32
+#ifndef MIN_STACK_ALIGN
+#define MIN_STACK_ALIGN (sizeof (uintptr_t))
 #endif
 
 #ifdef HAVE_CPU_CACHE_ALIGN
diff --git a/firmware/export/tcc780x.h b/firmware/export/tcc780x.h
index 8706fbbf6d..22ec03aa09 100644
--- a/firmware/export/tcc780x.h
+++ b/firmware/export/tcc780x.h
@@ -22,6 +22,7 @@
 #define __TCC780X_H__
 
 #define CACHEALIGN_BITS (5)
+#define CACHEALIGN_SIZE (32)
 
 #define TTB_SIZE      (0x4000)
 /* must be 16Kb (0x4000) aligned */
diff --git a/firmware/export/x1000.h b/firmware/export/x1000.h
index b71d37d64d..22e655eeaf 100644
--- a/firmware/export/x1000.h
+++ b/firmware/export/x1000.h
@@ -119,6 +119,7 @@
 
 /* CPU cache parameters */
 #define CACHEALIGN_BITS     5
+#define CACHEALIGN_SIZE     32
 #define CACHE_SIZE          (16 * 1024)
 
 #endif /* __X1000_H__ */
diff --git a/firmware/target/arm/pp/app-pp.lds b/firmware/target/arm/pp/app-pp.lds
index 3fdf55e332..dbeb175bce 100644
--- a/firmware/target/arm/pp/app-pp.lds
+++ b/firmware/target/arm/pp/app-pp.lds
@@ -1,3 +1,6 @@
+#define __ASSEMBLER__
+#include "cpu.h"
+
 /* Will have been included from app.lds */
 ENTRY(start)
 
@@ -20,8 +23,6 @@ STARTUP(target/arm/pp/crt0-pp.o)
 #define NOCACHE_BASE 	0x28000000
 #endif
 
-#define CACHEALIGN_SIZE 16
-
 /* End of the audio buffer, where the codec buffer starts */
 #define ENDAUDIOADDR  (DRAMORIG + DRAMSIZE)
 
diff --git a/firmware/target/arm/pp/boot-pp502x-bl-usb.lds b/firmware/target/arm/pp/boot-pp502x-bl-usb.lds
index 00fdb88230..8b4a271c62 100644
--- a/firmware/target/arm/pp/boot-pp502x-bl-usb.lds
+++ b/firmware/target/arm/pp/boot-pp502x-bl-usb.lds
@@ -1,3 +1,6 @@
+#define __ASSEMBLER__
+#include "cpu.h"
+
 /* Will have been included from boot.lds */
 ENTRY(start)
 OUTPUT_FORMAT(elf32-littlearm)
@@ -15,8 +18,6 @@ STARTUP(target/arm/pp/crt0-pp502x-bl-usb.o)
 #define FLASHORIG 0x001f0000
 #define FLASHSIZE 2M
 
-#define CACHEALIGN_SIZE 16
-
 MEMORY
 {
     DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
diff --git a/firmware/target/mips/ingenic_jz47xx/system-target.h b/firmware/target/mips/ingenic_jz47xx/system-target.h
index 1db0ee4671..968a738632 100644
--- a/firmware/target/mips/ingenic_jz47xx/system-target.h
+++ b/firmware/target/mips/ingenic_jz47xx/system-target.h
@@ -30,7 +30,6 @@
 #include "system-mips.h"
 
 #define CACHE_SIZE       16*1024
-#define CACHEALIGN_BITS  5
 #include "mmu-mips.h"
 
 #define CFG_UART_BASE    UART1_BASE      /* Base of the UART channel */
diff --git a/lib/rbcodec/codecs/lib/codeclib.c b/lib/rbcodec/codecs/lib/codeclib.c
index 12e29f477c..6e8c209489 100644
--- a/lib/rbcodec/codecs/lib/codeclib.c
+++ b/lib/rbcodec/codecs/lib/codeclib.c
@@ -35,7 +35,7 @@ static unsigned char* mallocbuf = NULL;
 
 int codec_init(void)
 {
-    /* codec_get_buffer() aligns the resulting point to CACHEALIGN_SIZE. */
+    /* codec_get_buffer() aligns the resulting point to MEM_ALIGN_SIZE. */
     mem_ptr = 0;
     mallocbuf = (unsigned char *)ci->codec_get_buffer((size_t *)&bufsize);
   
@@ -67,8 +67,8 @@ void* codec_malloc(size_t size)
     
     x=&mallocbuf[mem_ptr];
     
-    /* Keep memory aligned to CACHEALIGN_SIZE. */
-    mem_ptr += (size + (CACHEALIGN_SIZE-1)) & ~(CACHEALIGN_SIZE-1);
+    /* Keep memory aligned to MEM_ALIGN_SIZE. */
+    mem_ptr += MEM_ALIGN_UP(size);
 
     return(x);
 }
diff --git a/lib/rbcodec/codecs/libtremor/oggmalloc.c b/lib/rbcodec/codecs/libtremor/oggmalloc.c
index 31d88f191d..df045825e5 100644
--- a/lib/rbcodec/codecs/libtremor/oggmalloc.c
+++ b/lib/rbcodec/codecs/libtremor/oggmalloc.c
@@ -72,8 +72,8 @@ void iram_malloc_init(void){
 void *iram_malloc(size_t size){
     void* x;
 
-    /* always ensure alignment to CACHEALIGN_SIZE byte */
-    size = (size + (CACHEALIGN_SIZE-1)) & ~(CACHEALIGN_SIZE-1);
+    /* align for best performance */
+    size = MEM_ALIGN_UP(size);
 
     if(size>iram_remain)
       return NULL;
diff --git a/lib/rbcodec/platform.h b/lib/rbcodec/platform.h
index d6b890599a..1543f30e9b 100644
--- a/lib/rbcodec/platform.h
+++ b/lib/rbcodec/platform.h
@@ -117,9 +117,6 @@ size_t strlcpy(char *dst, const char *src, size_t siz);
 # define MEM_ALIGN_ATTR
 #endif
 
-#ifndef CACHEALIGN_SIZE
-# define CACHEALIGN_SIZE 1
-#endif
 /*
 #ifndef HAVE_CLIP_SAMPLE_16
 static inline int32_t clip_sample_16(int32_t sample)
diff --git a/lib/rbcodec/test/warble.c b/lib/rbcodec/test/warble.c
index 6f190e98de..fa243a3913 100644
--- a/lib/rbcodec/test/warble.c
+++ b/lib/rbcodec/test/warble.c
@@ -428,12 +428,9 @@ static void perform_config(void)
 
 static void *ci_codec_get_buffer(size_t *size)
 {
-    static char buffer[64 * 1024 * 1024];
-    char *ptr = buffer;
+    static char buffer[64 * 1024 * 1024] MEM_ALIGN_ATTR;
     *size = sizeof(buffer);
-    if ((intptr_t)ptr & (CACHEALIGN_SIZE - 1))
-        ptr += CACHEALIGN_SIZE - ((intptr_t)ptr & (CACHEALIGN_SIZE - 1));
-    return ptr;
+    return buffer;
 }
 
 static void ci_pcmbuf_insert(const void *ch1, const void *ch2, int count)
-- 
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