firmware: cleanup PortalPlayer NOCACHE_BASE defines

commit 99dd797169f688a0ffbd203c8c2069466a3826d1
Author: Aidan MacDonald <[email protected]>
Date:   Fri Mar 6 10:35:19 2026 +0000

    firmware: cleanup PortalPlayer NOCACHE_BASE defines
    
    Move the definition of NOCACHE_BASE to the CPU headers
    instead of having them copy-and-pasted in a few places.
    
    Change-Id: Ibbab27a5a07906d46dbd4dd9065f2238bc885d6b

diff --git a/apps/plugins/plugin.lds b/apps/plugins/plugin.lds
index 67ebe449e4..b36afbf4b0 100644
--- a/apps/plugins/plugin.lds
+++ b/apps/plugins/plugin.lds
@@ -15,14 +15,6 @@ OUTPUT_FORMAT(elf32-littlemips)
 #error Unknown CPU architecture
 #endif
 
-#if defined(CPU_PP)
-#ifdef CPU_PP502x
-#define NOCACHE_BASE 	0x10000000
-#else
-#define NOCACHE_BASE 	0x28000000
-#endif /* CPU_* */
-#endif /* CPU_PP */
-
 #if CONFIG_CPU==IMX31L
 #define DRAMSIZE ((MEMORYSIZE * 0x100000) - PLUGIN_BUFFER_SIZE \
                   - CODEC_SIZE - QHARRAY_SIZE - FRAME_SIZE - TTB_SIZE)
@@ -194,11 +186,6 @@ OUTPUT_FORMAT(elf32-littlemips)
 # error "DRAMORIG not defined!"
 #endif
 
-#ifndef NOCACHE_BASE
-/* Default to no offset if target doesn't define this */
-#define NOCACHE_BASE 0x00000000
-#endif
-
 #define PLUGIN_LENGTH PLUGIN_BUFFER_SIZE
 
 
@@ -268,7 +255,7 @@ SECTIONS
 #endif
     } > PLUGIN_RAM
 
-#if NOCACHE_BASE != 0
+#if defined(NOCACHE_BASE)
     /*
      * Allocate .ncdata based on the following constraints:
      *
@@ -304,7 +291,7 @@ SECTIONS
         . = ALIGN(0x4);
     } > PLUGIN_RAM
 
-#if NOCACHE_BASE != 0
+#if defined(NOCACHE_BASE)
     /*
      * .ncbss has the same constraints as the .ncdata section
      * above but there is an extra complication: because it is
@@ -385,7 +372,7 @@ SECTIONS
     }
 }
 
-#if NOCACHE_BASE != 0
+#if defined(NOCACHE_BASE)
 /* Some asserts to make sure nocache sections appear correctly defined */
 ASSERT(LOADADDR(.ncdata) == ADDR(.ncdata) - NOCACHE_BASE, ".ncdata has incorrect LMA/VMA address");
 ASSERT(LOADADDR(.ncdata) % CACHEALIGN_SIZE == 0,          ".ncdata incorrectly aligned");
diff --git a/firmware/export/cpu.h b/firmware/export/cpu.h
index f064a96c72..6c817ad46d 100644
--- a/firmware/export/cpu.h
+++ b/firmware/export/cpu.h
@@ -81,4 +81,25 @@
 # endif
 #endif
 
+/*
+ * Note: NOCACHE_BASE assumes that DRAM is linearly mapped both
+ * at a lower cached address and an upper uncached address, so
+ * that you can add NOCACHE_BASE to the cached DRAM address to
+ * get the corresponding uncached address.
+ *
+ * Defining NOCACHE_BASE is only required if you need plugins to
+ * be able to link data at uncached addresses. If in doubt, you
+ * don't need this. It's mainly of use for dual-core PortalPlayer
+ * targets which need to do this for things like mutexes/queues;
+ * since PP lacks hardware cache coherency, data which is writable
+ * by more than one core often needs to accessed uncached.
+ */
+#if defined(NOCACHE_BASE)
+# if !defined(HAVE_CPU_CACHE_ALIGN)
+#  error "NOCACHE_BASE cannot be defined on targets with no CPU cache!"
+# elif NOCACHE_BASE == 0
+#  error "NOCACHE_BASE cannot be 0!"
+# endif
+#endif
+
 #endif /* __CPU_H */
diff --git a/firmware/export/pp5002.h b/firmware/export/pp5002.h
index 62a65a3d2e..5cfc0c5442 100644
--- a/firmware/export/pp5002.h
+++ b/firmware/export/pp5002.h
@@ -27,6 +27,7 @@
 #define CACHEALIGN_SIZE (16)
 
 #define DRAM_START       0x28000000
+#define NOCACHE_BASE     0x28000000
 
 /* LCD bridge */
 #define LCD1_BASE        0xc0001000
diff --git a/firmware/export/pp5020.h b/firmware/export/pp5020.h
index c15d50ee38..04bd7c44f3 100644
--- a/firmware/export/pp5020.h
+++ b/firmware/export/pp5020.h
@@ -38,6 +38,7 @@
 
 /* DRAM starts at 0x10000000, but in Rockbox we remap it to 0x00000000 */
 #define DRAM_START       0x10000000
+#define NOCACHE_BASE     0x10000000
 
 /* Processor ID */
 #define PROCESSOR_ID     (*(volatile unsigned long *)(0x60000000))
diff --git a/firmware/target/arm/pp/app-pp.lds b/firmware/target/arm/pp/app-pp.lds
index dbeb175bce..4ed86070ab 100644
--- a/firmware/target/arm/pp/app-pp.lds
+++ b/firmware/target/arm/pp/app-pp.lds
@@ -17,12 +17,6 @@ STARTUP(target/arm/pp/crt0-pp.o)
 #define IRAMORIG 0x40000000
 #define IRAMSIZE 0xc000
 
-#ifdef CPU_PP502x
-#define NOCACHE_BASE 	0x10000000
-#else
-#define NOCACHE_BASE 	0x28000000
-#endif
-
 /* End of the audio buffer, where the codec buffer starts */
 #define ENDAUDIOADDR  (DRAMORIG + DRAMSIZE)
 
diff --git a/firmware/target/arm/pp/boot-pp502x-bl-usb.lds b/firmware/target/arm/pp/boot-pp502x-bl-usb.lds
index 8b4a271c62..8485635dbe 100644
--- a/firmware/target/arm/pp/boot-pp502x-bl-usb.lds
+++ b/firmware/target/arm/pp/boot-pp502x-bl-usb.lds
@@ -10,7 +10,6 @@ STARTUP(target/arm/pp/crt0-pp502x-bl-usb.o)
 #define DRAMORIG        0x01000000 /* Load at 16 MB */
 #define DRAMSIZE        0x00100000 /* 1MB for bootloader */
 #define MEMEND          (MEMORYSIZE*0x100000) /* From virtual mapping at 0 */
-#define NOCACHE_BASE    0x10000000
 #ifndef IRAMORIG
 #define IRAMORIG 0x40000000
 #endif
-- 
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