fix incompatible pointer errors with clang
rockbox-gerrit-noreply--- via rockbox-cvs <[email protected]> Wed, 27 May 2026 08:43:56 -0400
| Newsgroups | gmane.comp.systems.archos.rockbox.cvs |
|---|---|
| Message-ID | <[email protected]> |
commit 6e31703289a671d8d6a476a0329f52e9a3eabf90 Author: mojyack <[email protected]> Date: Mon May 4 20:03:47 2026 +0900 fix incompatible pointer errors with clang clang uses "unsigned int" for "uint32_t", which does not match gcc's "unsigned long". fix errors caused by this. Change-Id: I05aaf23934167a56a6e400f49fcaf8b70bfaca13 diff --git a/firmware/drivers/rtc/rtc_imx233.c b/firmware/drivers/rtc/rtc_imx233.c index 72f11a78c8..29fb7a709b 100644 --- a/firmware/drivers/rtc/rtc_imx233.c +++ b/firmware/drivers/rtc/rtc_imx233.c @@ -38,7 +38,7 @@ void rtc_init(void) /* rtc-imx233 is initialized by the system */ } -static void seconds_to_datetime(uint32_t seconds, struct tm *tm) +static void seconds_to_datetime(time_t seconds, struct tm *tm) { #ifdef USE_PERSISTENT /* The OF uses PERSISTENT2 register to keep the adjustment and only changes diff --git a/firmware/drivers/rtc/rtc_mc13783.c b/firmware/drivers/rtc/rtc_mc13783.c index aedf5f6fa5..867a8f7a0a 100644 --- a/firmware/drivers/rtc/rtc_mc13783.c +++ b/firmware/drivers/rtc/rtc_mc13783.c @@ -69,7 +69,7 @@ static const unsigned char rtc_registers[RTC_NUM_REGS_RD] = /* was it an alarm that triggered power on ? */ static bool alarm_start = false; -static unsigned long rtc_is_dirty = 1; /* force a read right away */ +static uint32_t rtc_is_dirty = 1; /* force a read right away */ static const unsigned short month_table[13] = { diff --git a/firmware/export/as3525.h b/firmware/export/as3525.h index 0d4b02844d..9b6e059b53 100644 --- a/firmware/export/as3525.h +++ b/firmware/export/as3525.h @@ -20,6 +20,10 @@ #ifndef __AS3525_H__ #define __AS3525_H__ +#if !defined(__ASSEMBLER__) +#include <stdint.h> +#endif + #define CACHEALIGN_BITS (5) #define CACHEALIGN_SIZE (32) @@ -103,26 +107,26 @@ ------------------------------------------------------------------------ */ -#define CCU_SRC (*(volatile unsigned long *)(CCU_BASE + 0x00)) -#define CCU_SRL (*(volatile unsigned long *)(CCU_BASE + 0x04)) -#define CCU_MEMMAP (*(volatile unsigned long *)(CCU_BASE + 0x08)) -#define CCU_IO (*(volatile unsigned long *)(CCU_BASE + 0x0C)) -#define CCU_SCON (*(volatile unsigned long *)(CCU_BASE + 0x10)) -#define CCU_VERS (*(volatile unsigned long *)(CCU_BASE + 0x14)) -#define CCU_SPARE1 (*(volatile unsigned long *)(CCU_BASE + 0x18)) -#define CCU_SPARE2 (*(volatile unsigned long *)(CCU_BASE + 0x1C)) +#define CCU_SRC (*(volatile uint32_t*)(CCU_BASE + 0x00)) +#define CCU_SRL (*(volatile uint32_t*)(CCU_BASE + 0x04)) +#define CCU_MEMMAP (*(volatile uint32_t*)(CCU_BASE + 0x08)) +#define CCU_IO (*(volatile uint32_t*)(CCU_BASE + 0x0C)) +#define CCU_SCON (*(volatile uint32_t*)(CCU_BASE + 0x10)) +#define CCU_VERS (*(volatile uint32_t*)(CCU_BASE + 0x14)) +#define CCU_SPARE1 (*(volatile uint32_t*)(CCU_BASE + 0x18)) +#define CCU_SPARE2 (*(volatile uint32_t*)(CCU_BASE + 0x1C)) /* DBOP */ -#define DBOP_TIMPOL_01 (*(volatile unsigned long *)(DBOP_BASE + 0x00)) -#define DBOP_TIMPOL_23 (*(volatile unsigned long *)(DBOP_BASE + 0x04)) -#define DBOP_CTRL (*(volatile unsigned long *)(DBOP_BASE + 0x08)) -#define DBOP_STAT (*(volatile unsigned long *)(DBOP_BASE + 0x0C)) +#define DBOP_TIMPOL_01 (*(volatile uint32_t*)(DBOP_BASE + 0x00)) +#define DBOP_TIMPOL_23 (*(volatile uint32_t*)(DBOP_BASE + 0x04)) +#define DBOP_CTRL (*(volatile uint32_t*)(DBOP_BASE + 0x08)) +#define DBOP_STAT (*(volatile uint32_t*)(DBOP_BASE + 0x0C)) /* default is 16bit, but we switch to 32bit for some targets for better speed */ -#define DBOP_DOUT8 (*(volatile unsigned char*)(DBOP_BASE + 0x10)) -#define DBOP_DOUT (*(volatile unsigned short*)(DBOP_BASE + 0x10)) -#define DBOP_DOUT16 (*(volatile unsigned short*)(DBOP_BASE + 0x10)) -#define DBOP_DOUT32 (*(volatile unsigned long *)(DBOP_BASE + 0x10)) -#define DBOP_DIN (*(volatile unsigned short*)(DBOP_BASE + 0x14)) +#define DBOP_DOUT8 (*(volatile uint8_t*)(DBOP_BASE + 0x10)) +#define DBOP_DOUT (*(volatile uint16_t*)(DBOP_BASE + 0x10)) +#define DBOP_DOUT16 (*(volatile uint16_t*)(DBOP_BASE + 0x10)) +#define DBOP_DOUT32 (*(volatile uint32_t*)(DBOP_BASE + 0x10)) +#define DBOP_DIN (*(volatile uint16_t*)(DBOP_BASE + 0x14)) /** @@ -205,21 +209,21 @@ CE lines ------------------------------------------------------------------------ */ -#define CGU_PLLA (*(volatile unsigned long *)(CGU_BASE + 0x00)) -#define CGU_PLLB (*(volatile unsigned long *)(CGU_BASE + 0x04)) -#define CGU_PLLASUP (*(volatile unsigned long *)(CGU_BASE + 0x08)) -#define CGU_PLLBSUP (*(volatile unsigned long *)(CGU_BASE + 0x0C)) -#define CGU_PROC (*(volatile unsigned long *)(CGU_BASE + 0x10)) -#define CGU_PERI (*(volatile unsigned long *)(CGU_BASE + 0x14)) -#define CGU_AUDIO (*(volatile unsigned long *)(CGU_BASE + 0x18)) -#define CGU_USB (*(volatile unsigned long *)(CGU_BASE + 0x1C)) -#define CGU_INTCTRL (*(volatile unsigned long *)(CGU_BASE + 0x20)) -#define CGU_IRQ (*(volatile unsigned long *)(CGU_BASE + 0x24)) -#define CGU_COUNTA (*(volatile unsigned long *)(CGU_BASE + 0x28)) -#define CGU_COUNTB (*(volatile unsigned long *)(CGU_BASE + 0x2C)) -#define CGU_IDE (*(volatile unsigned long *)(CGU_BASE + 0x30)) -#define CGU_MEMSTICK (*(volatile unsigned long *)(CGU_BASE + 0x34)) -#define CGU_DBOP (*(volatile unsigned long *)(CGU_BASE + 0x38)) +#define CGU_PLLA (*(volatile uint32_t*)(CGU_BASE + 0x00)) +#define CGU_PLLB (*(volatile uint32_t*)(CGU_BASE + 0x04)) +#define CGU_PLLASUP (*(volatile uint32_t*)(CGU_BASE + 0x08)) +#define CGU_PLLBSUP (*(volatile uint32_t*)(CGU_BASE + 0x0C)) +#define CGU_PROC (*(volatile uint32_t*)(CGU_BASE + 0x10)) +#define CGU_PERI (*(volatile uint32_t*)(CGU_BASE + 0x14)) +#define CGU_AUDIO (*(volatile uint32_t*)(CGU_BASE + 0x18)) +#define CGU_USB (*(volatile uint32_t*)(CGU_BASE + 0x1C)) +#define CGU_INTCTRL (*(volatile uint32_t*)(CGU_BASE + 0x20)) +#define CGU_IRQ (*(volatile uint32_t*)(CGU_BASE + 0x24)) +#define CGU_COUNTA (*(volatile uint32_t*)(CGU_BASE + 0x28)) +#define CGU_COUNTB (*(volatile uint32_t*)(CGU_BASE + 0x2C)) +#define CGU_IDE (*(volatile uint32_t*)(CGU_BASE + 0x30)) +#define CGU_MEMSTICK (*(volatile uint32_t*)(CGU_BASE + 0x34)) +#define CGU_DBOP (*(volatile uint32_t*)(CGU_BASE + 0x38)) #define CGU_VIC_CLOCK_ENABLE ( 1 << 23 ) /* vic */ /* --- are disabled after reset --- */ @@ -297,35 +301,35 @@ CE lines -#define UART_DATA_REG (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Data register */ -#define UART_DLO_REG (*(volatile unsigned long*)(UART0_BASE + 0x00)) /* Clock divider(lower byte) register */ -#define UART_DHI_REG (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Clock divider(higher byte) register */ -#define UART_INTEN_REG (*(volatile unsigned long*)(UART0_BASE + 0x04)) /* Interrupt enable register */ -#define UART_INTSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x08)) /* Interrupt status register */ -#define UART_FCTL_REG (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo control register */ -#define UART_FSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x0C)) /* Fifo status register */ -#define UART_LNCTL_REG (*(volatile unsigned long*)(UART0_BASE + 0x10)) /* Line control register */ -#define UART_LNSTATUS_REG (*(volatile unsigned long*)(UART0_BASE + 0x14)) /* Line status register */ +#define UART_DATA_REG (*(volatile uint32_t*)(UART0_BASE + 0x00)) /* Data register */ +#define UART_DLO_REG (*(volatile uint32_t*)(UART0_BASE + 0x00)) /* Clock divider(lower byte) register */ +#define UART_DHI_REG (*(volatile uint32_t*)(UART0_BASE + 0x04)) /* Clock divider(higher byte) register */ +#define UART_INTEN_REG (*(volatile uint32_t*)(UART0_BASE + 0x04)) /* Interrupt enable register */ +#define UART_INTSTATUS_REG (*(volatile uint32_t*)(UART0_BASE + 0x08)) /* Interrupt status register */ +#define UART_FCTL_REG (*(volatile uint32_t*)(UART0_BASE + 0x0C)) /* Fifo control register */ +#define UART_FSTATUS_REG (*(volatile uint32_t*)(UART0_BASE + 0x0C)) /* Fifo status register */ +#define UART_LNCTL_REG (*(volatile uint32_t*)(UART0_BASE + 0x10)) /* Line control register */ +#define UART_LNSTATUS_REG (*(volatile uint32_t*)(UART0_BASE + 0x14)) /* Line status register */ -#define SD_MCI_POWER (*(volatile unsigned long*)(SD_MCI_BASE + 0x0)) +#define SD_MCI_POWER (*(volatile uint32_t*)(SD_MCI_BASE + 0x0)) -#define TIMER1_LOAD (*(volatile unsigned long*)(TIMER_BASE + 0x00)) /* 32-bit width */ -#define TIMER1_VALUE (*(volatile unsigned long*)(TIMER_BASE + 0x04)) /* 32 bit width */ -#define TIMER1_CONTROL (*(volatile unsigned long*)(TIMER_BASE + 0x08)) /* 8 bit width */ -#define TIMER1_INTCLR (*(volatile unsigned long*)(TIMER_BASE + 0x0C)) /* clears ir by write access */ -#define TIMER1_RIS (*(volatile unsigned long*)(TIMER_BASE + 0x10)) /* 1 bit width */ -#define TIMER1_MIS (*(volatile unsigned long*)(TIMER_BASE + 0x14)) /* 1 bit width */ -#define TIMER1_BGLOAD (*(volatile unsigned long*)(TIMER_BASE + 0x18)) /* 32-bit width */ +#define TIMER1_LOAD (*(volatile uint32_t*)(TIMER_BASE + 0x00)) /* 32-bit width */ +#define TIMER1_VALUE (*(volatile uint32_t*)(TIMER_BASE + 0x04)) /* 32 bit width */ +#define TIMER1_CONTROL (*(volatile uint32_t*)(TIMER_BASE + 0x08)) /* 8 bit width */ +#define TIMER1_INTCLR (*(volatile uint32_t*)(TIMER_BASE + 0x0C)) /* clears ir by write access */ +#define TIMER1_RIS (*(volatile uint32_t*)(TIMER_BASE + 0x10)) /* 1 bit width */ +#define TIMER1_MIS (*(volatile uint32_t*)(TIMER_BASE + 0x14)) /* 1 bit width */ +#define TIMER1_BGLOAD (*(volatile uint32_t*)(TIMER_BASE + 0x18)) /* 32-bit width */ -#define TIMER2_LOAD (*(volatile unsigned long*)(TIMER_BASE + 0x20)) /* 32-bit width */ -#define TIMER2_VALUE (*(volatile unsigned long*)(TIMER_BASE + 0x24)) /* 32 bit width */ -#define TIMER2_CONTROL (*(volatile unsigned long*)(TIMER_BASE + 0x28)) /* 8 bit width */ -#define TIMER2_INTCLR (*(volatile unsigned long*)(TIMER_BASE + 0x2C)) /* clears ir by write access */ -#define TIMER2_RIS (*(volatile unsigned long*)(TIMER_BASE + 0x30)) /* 1 bit width */ -#define TIMER2_MIS (*(volatile unsigned long*)(TIMER_BASE + 0x34)) /* 1 bit width */ -#define TIMER2_BGLOAD (*(volatile unsigned long*)(TIMER_BASE + 0x38)) /* 32-bit width */ +#define TIMER2_LOAD (*(volatile uint32_t*)(TIMER_BASE + 0x20)) /* 32-bit width */ +#define TIMER2_VALUE (*(volatile uint32_t*)(TIMER_BASE + 0x24)) /* 32 bit width */ +#define TIMER2_CONTROL (*(volatile uint32_t*)(TIMER_BASE + 0x28)) /* 8 bit width */ +#define TIMER2_INTCLR (*(volatile uint32_t*)(TIMER_BASE + 0x2C)) /* clears ir by write access */ +#define TIMER2_RIS (*(volatile uint32_t*)(TIMER_BASE + 0x30)) /* 1 bit width */ +#define TIMER2_MIS (*(volatile uint32_t*)(TIMER_BASE + 0x34)) /* 1 bit width */ +#define TIMER2_BGLOAD (*(volatile uint32_t*)(TIMER_BASE + 0x38)) /* 32-bit width */ /** * Counter/Timer control register bits @@ -341,114 +345,114 @@ CE lines /* Watchdog registers */ -#define WDT_LOAD (*(volatile unsigned long*)(WDT_BASE)) -#define WDT_CONTROL (*(volatile unsigned long*)(WDT_BASE+8)) +#define WDT_LOAD (*(volatile uint32_t*)(WDT_BASE)) +#define WDT_CONTROL (*(volatile uint32_t*)(WDT_BASE+8)) /* GPIO registers */ -#define GPIOA_DIR (*(volatile unsigned char*)(GPIOA_BASE+0x400)) -#define GPIOA_IS (*(volatile unsigned char*)(GPIOA_BASE+0x404)) -#define GPIOA_IBE (*(volatile unsigned char*)(GPIOA_BASE+0x408)) -#define GPIOA_IEV (*(volatile unsigned char*)(GPIOA_BASE+0x40C)) -#define GPIOA_IE (*(volatile unsigned char*)(GPIOA_BASE+0x410)) -#define GPIOA_RIS (*(volatile unsigned char*)(GPIOA_BASE+0x414)) -#define GPIOA_MIS (*(volatile unsigned char*)(GPIOA_BASE+0x418)) -#define GPIOA_IC (*(volatile unsigned char*)(GPIOA_BASE+0x41C)) -#define GPIOA_AFSEL (*(volatile unsigned char*)(GPIOA_BASE+0x420)) -#define GPIOA_PIN(a) (*(volatile unsigned char*)(GPIOA_BASE+(1<<((a)+2)))) -#define GPIOA_PIN_MASK(m) (*(volatile unsigned char *)(GPIOA_BASE+(((m)&0xff)<<2))) -#define GPIOA_DATA (*(volatile unsigned char*)(GPIOA_BASE+(0xff<<2))) - - -#define GPIOB_DIR (*(volatile unsigned char*)(GPIOB_BASE+0x400)) -#define GPIOB_IS (*(volatile unsigned char*)(GPIOB_BASE+0x404)) -#define GPIOB_IBE (*(volatile unsigned char*)(GPIOB_BASE+0x408)) -#define GPIOB_IEV (*(volatile unsigned char*)(GPIOB_BASE+0x40C)) -#define GPIOB_IE (*(volatile unsigned char*)(GPIOB_BASE+0x410)) -#define GPIOB_RIS (*(volatile unsigned char*)(GPIOB_BASE+0x414)) -#define GPIOB_MIS (*(volatile unsigned char*)(GPIOB_BASE+0x418)) -#define GPIOB_IC (*(volatile unsigned char*)(GPIOB_BASE+0x41C)) -#define GPIOB_AFSEL (*(volatile unsigned char*)(GPIOB_BASE+0x420)) -#define GPIOB_PIN(a) (*(volatile unsigned char*)(GPIOB_BASE+(1<<((a)+2)))) -#define GPIOB_PIN_MASK(m) (*(volatile unsigned char *)(GPIOB_BASE+(((m)&0xff)<<2))) -#define GPIOB_DATA (*(volatile unsigned char*)(GPIOB_BASE+(0xff<<2))) - -#define GPIOC_DIR (*(volatile unsigned char*)(GPIOC_BASE+0x400)) -#define GPIOC_IS (*(volatile unsigned char*)(GPIOC_BASE+0x404)) -#define GPIOC_IBE (*(volatile unsigned char*)(GPIOC_BASE+0x408)) -#define GPIOC_IEV (*(volatile unsigned char*)(GPIOC_BASE+0x40C)) -#define GPIOC_IE (*(volatile unsigned char*)(GPIOC_BASE+0x410)) -#define GPIOC_RIS (*(volatile unsigned char*)(GPIOC_BASE+0x414)) -#define GPIOC_MIS (*(volatile unsigned char*)(GPIOC_BASE+0x418)) -#define GPIOC_IC (*(volatile unsigned char*)(GPIOC_BASE+0x41C)) -#define GPIOC_AFSEL (*(volatile unsigned char*)(GPIOC_BASE+0x420)) -#define GPIOC_PIN(a) (*(volatile unsigned char*)(GPIOC_BASE+(1<<((a)+2)))) -#define GPIOC_PIN_MASK(m) (*(volatile unsigned char *)(GPIOC_BASE+(((m)&0xff)<<2))) -#define GPIOC_DATA (*(volatile unsigned char*)(GPIOC_BASE+(0xff<<2))) - -#define GPIOD_DIR (*(volatile unsigned char*)(GPIOD_BASE+0x400)) -#define GPIOD_IS (*(volatile unsigned char*)(GPIOD_BASE+0x404)) -#define GPIOD_IBE (*(volatile unsigned char*)(GPIOD_BASE+0x408)) -#define GPIOD_IEV (*(volatile unsigned char*)(GPIOD_BASE+0x40C)) -#define GPIOD_IE (*(volatile unsigned char*)(GPIOD_BASE+0x410)) -#define GPIOD_RIS (*(volatile unsigned char*)(GPIOD_BASE+0x414)) -#define GPIOD_MIS (*(volatile unsigned char*)(GPIOD_BASE+0x418)) -#define GPIOD_IC (*(volatile unsigned char*)(GPIOD_BASE+0x41C)) -#define GPIOD_AFSEL (*(volatile unsigned char*)(GPIOD_BASE+0x420)) -#define GPIOD_PIN(a) (*(volatile unsigned char*)(GPIOD_BASE+(1<<((a)+2)))) -#define GPIOD_PIN_MASK(m) (*(volatile unsigned char *)(GPIOD_BASE+(((m)&0xff)<<2))) -#define GPIOD_DATA (*(volatile unsigned char*)(GPIOD_BASE+(0xff<<2))) +#define GPIOA_DIR (*(volatile uint8_t*)(GPIOA_BASE+0x400)) +#define GPIOA_IS (*(volatile uint8_t*)(GPIOA_BASE+0x404)) +#define GPIOA_IBE (*(volatile uint8_t*)(GPIOA_BASE+0x408)) +#define GPIOA_IEV (*(volatile uint8_t*)(GPIOA_BASE+0x40C)) +#define GPIOA_IE (*(volatile uint8_t*)(GPIOA_BASE+0x410)) +#define GPIOA_RIS (*(volatile uint8_t*)(GPIOA_BASE+0x414)) +#define GPIOA_MIS (*(volatile uint8_t*)(GPIOA_BASE+0x418)) +#define GPIOA_IC (*(volatile uint8_t*)(GPIOA_BASE+0x41C)) +#define GPIOA_AFSEL (*(volatile uint8_t*)(GPIOA_BASE+0x420)) +#define GPIOA_PIN(a) (*(volatile uint8_t*)(GPIOA_BASE+(1<<((a)+2)))) +#define GPIOA_PIN_MASK(m) (*(volatile uint8_t*)(GPIOA_BASE+(((m)&0xff)<<2))) +#define GPIOA_DATA (*(volatile uint8_t*)(GPIOA_BASE+(0xff<<2))) + + +#define GPIOB_DIR (*(volatile uint8_t*)(GPIOB_BASE+0x400)) +#define GPIOB_IS (*(volatile uint8_t*)(GPIOB_BASE+0x404)) +#define GPIOB_IBE (*(volatile uint8_t*)(GPIOB_BASE+0x408)) +#define GPIOB_IEV (*(volatile uint8_t*)(GPIOB_BASE+0x40C)) +#define GPIOB_IE (*(volatile uint8_t*)(GPIOB_BASE+0x410)) +#define GPIOB_RIS (*(volatile uint8_t*)(GPIOB_BASE+0x414)) +#define GPIOB_MIS (*(volatile uint8_t*)(GPIOB_BASE+0x418)) +#define GPIOB_IC (*(volatile uint8_t*)(GPIOB_BASE+0x41C)) +#define GPIOB_AFSEL (*(volatile uint8_t*)(GPIOB_BASE+0x420)) +#define GPIOB_PIN(a) (*(volatile uint8_t*)(GPIOB_BASE+(1<<((a)+2)))) +#define GPIOB_PIN_MASK(m) (*(volatile uint8_t*)(GPIOB_BASE+(((m)&0xff)<<2))) +#define GPIOB_DATA (*(volatile uint8_t*)(GPIOB_BASE+(0xff<<2))) + +#define GPIOC_DIR (*(volatile uint8_t*)(GPIOC_BASE+0x400)) +#define GPIOC_IS (*(volatile uint8_t*)(GPIOC_BASE+0x404)) +#define GPIOC_IBE (*(volatile uint8_t*)(GPIOC_BASE+0x408)) +#define GPIOC_IEV (*(volatile uint8_t*)(GPIOC_BASE+0x40C)) +#define GPIOC_IE (*(volatile uint8_t*)(GPIOC_BASE+0x410)) +#define GPIOC_RIS (*(volatile uint8_t*)(GPIOC_BASE+0x414)) +#define GPIOC_MIS (*(volatile uint8_t*)(GPIOC_BASE+0x418)) +#define GPIOC_IC (*(volatile uint8_t*)(GPIOC_BASE+0x41C)) +#define GPIOC_AFSEL (*(volatile uint8_t*)(GPIOC_BASE+0x420)) +#define GPIOC_PIN(a) (*(volatile uint8_t*)(GPIOC_BASE+(1<<((a)+2)))) +#define GPIOC_PIN_MASK(m) (*(volatile uint8_t*)(GPIOC_BASE+(((m)&0xff)<<2))) +#define GPIOC_DATA (*(volatile uint8_t*)(GPIOC_BASE+(0xff<<2))) + +#define GPIOD_DIR (*(volatile uint8_t*)(GPIOD_BASE+0x400)) +#define GPIOD_IS (*(volatile uint8_t*)(GPIOD_BASE+0x404)) +#define GPIOD_IBE (*(volatile uint8_t*)(GPIOD_BASE+0x408)) +#define GPIOD_IEV (*(volatile uint8_t*)(GPIOD_BASE+0x40C)) +#define GPIOD_IE (*(volatile uint8_t*)(GPIOD_BASE+0x410)) +#define GPIOD_RIS (*(volatile uint8_t*)(GPIOD_BASE+0x414)) +#define GPIOD_MIS (*(volatile uint8_t*)(GPIOD_BASE+0x418)) +#define GPIOD_IC (*(volatile uint8_t*)(GPIOD_BASE+0x41C)) +#define GPIOD_AFSEL (*(volatile uint8_t*)(GPIOD_BASE+0x420)) +#define GPIOD_PIN(a) (*(volatile uint8_t*)(GPIOD_BASE+(1<<((a)+2)))) +#define GPIOD_PIN_MASK(m) (*(volatile uint8_t*)(GPIOD_BASE+(((m)&0xff)<<2))) +#define GPIOD_DATA (*(volatile uint8_t*)(GPIOD_BASE+(0xff<<2))) /* ARM PL172 Memory Controller registers */ -#define MPMC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x000)) -#define MPMC_STATUS (*(volatile unsigned long*)(MPMC_BASE+0x004)) -#define MPMC_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x008)) - -#define MPMC_DYNAMIC_CONTROL (*(volatile unsigned long*)(MPMC_BASE+0x020)) -#define MPMC_DYNAMIC_REFRESH (*(volatile unsigned long*)(MPMC_BASE+0x024)) -#define MPMC_DYNAMIC_READ_CONFIG (*(volatile unsigned long*)(MPMC_BASE+0x028)) -#define MPMC_DYNAMIC_tRP (*(volatile unsigned long*)(MPMC_BASE+0x030)) -#define MPMC_DYNAMIC_tRAS (*(volatile unsigned long*)(MPMC_BASE+0x034)) -#define MPMC_DYNAMIC_tSREX (*(volatile unsigned long*)(MPMC_BASE+0x038)) -#define MPMC_DYNAMIC_tAPR (*(volatile unsigned long*)(MPMC_BASE+0x03C)) -#define MPMC_DYNAMIC_tDAL (*(volatile unsigned long*)(MPMC_BASE+0x040)) -#define MPMC_DYNAMIC_tWR (*(volatile unsigned long*)(MPMC_BASE+0x044)) -#define MPMC_DYNAMIC_tRC (*(volatile unsigned long*)(MPMC_BASE+0x048)) -#define MPMC_DYNAMIC_tRFC (*(volatile unsigned long*)(MPMC_BASE+0x04C)) -#define MPMC_DYNAMIC_tXSR (*(volatile unsigned long*)(MPMC_BASE+0x050)) -#define MPMC_DYNAMIC_tRRD (*(volatile unsigned long*)(MPMC_BASE+0x054)) -#define MPMC_DYNAMIC_tMRD (*(volatile unsigned long*)(MPMC_BASE+0x058)) - -#define MPMC_STATIC_EXTENDED_WAIT (*(volatile unsigned long*)(MPMC_BASE+0x080)) - -#define MPMC_DYNAMIC_CONFIG_0 (*(volatile unsigned long*)(MPMC_BASE+0x100)) -#define MPMC_DYNAMIC_CONFIG_1 (*(volatile unsigned long*)(MPMC_BASE+0x120)) -#define MPMC_DYNAMIC_CONFIG_2 (*(volatile unsigned long*)(MPMC_BASE+0x140)) -#define MPMC_DYNAMIC_CONFIG_3 (*(volatile unsigned long*)(MPMC_BASE+0x160)) - -#define MPMC_DYNAMIC_RASCAS_0 (*(volatile unsigned long*)(MPMC_BASE+0x104)) -#define MPMC_DYNAMIC_RASCAS_1 (*(volatile unsigned long*)(MPMC_BASE+0x124)) -#define MPMC_DYNAMIC_RASCAS_2 (*(volatile unsigned long*)(MPMC_BASE+0x144)) -#define MPMC_DYNAMIC_RASCAS_3 (*(volatile unsigned long*)(MPMC_BASE+0x164)) - -#define MPMC_PERIPH_ID2 (*(volatile unsigned long*)(MPMC_BASE+0xFE8)) +#define MPMC_CONTROL (*(volatile uint32_t*)(MPMC_BASE+0x000)) +#define MPMC_STATUS (*(volatile uint32_t*)(MPMC_BASE+0x004)) +#define MPMC_CONFIG (*(volatile uint32_t*)(MPMC_BASE+0x008)) + +#define MPMC_DYNAMIC_CONTROL (*(volatile uint32_t*)(MPMC_BASE+0x020)) +#define MPMC_DYNAMIC_REFRESH (*(volatile uint32_t*)(MPMC_BASE+0x024)) +#define MPMC_DYNAMIC_READ_CONFIG (*(volatile uint32_t*)(MPMC_BASE+0x028)) +#define MPMC_DYNAMIC_tRP (*(volatile uint32_t*)(MPMC_BASE+0x030)) +#define MPMC_DYNAMIC_tRAS (*(volatile uint32_t*)(MPMC_BASE+0x034)) +#define MPMC_DYNAMIC_tSREX (*(volatile uint32_t*)(MPMC_BASE+0x038)) +#define MPMC_DYNAMIC_tAPR (*(volatile uint32_t*)(MPMC_BASE+0x03C)) +#define MPMC_DYNAMIC_tDAL (*(volatile uint32_t*)(MPMC_BASE+0x040)) +#define MPMC_DYNAMIC_tWR (*(volatile uint32_t*)(MPMC_BASE+0x044)) +#define MPMC_DYNAMIC_tRC (*(volatile uint32_t*)(MPMC_BASE+0x048)) +#define MPMC_DYNAMIC_tRFC (*(volatile uint32_t*)(MPMC_BASE+0x04C)) +#define MPMC_DYNAMIC_tXSR (*(volatile uint32_t*)(MPMC_BASE+0x050)) +#define MPMC_DYNAMIC_tRRD (*(volatile uint32_t*)(MPMC_BASE+0x054)) +#define MPMC_DYNAMIC_tMRD (*(volatile uint32_t*)(MPMC_BASE+0x058)) + +#define MPMC_STATIC_EXTENDED_WAIT (*(volatile uint32_t*)(MPMC_BASE+0x080)) + +#define MPMC_DYNAMIC_CONFIG_0 (*(volatile uint32_t*)(MPMC_BASE+0x100)) +#define MPMC_DYNAMIC_CONFIG_1 (*(volatile uint32_t*)(MPMC_BASE+0x120)) +#define MPMC_DYNAMIC_CONFIG_2 (*(volatile uint32_t*)(MPMC_BASE+0x140)) +#define MPMC_DYNAMIC_CONFIG_3 (*(volatile uint32_t*)(MPMC_BASE+0x160)) + +#define MPMC_DYNAMIC_RASCAS_0 (*(volatile uint32_t*)(MPMC_BASE+0x104)) +#define MPMC_DYNAMIC_RASCAS_1 (*(volatile uint32_t*)(MPMC_BASE+0x124)) +#define MPMC_DYNAMIC_RASCAS_2 (*(volatile uint32_t*)(MPMC_BASE+0x144)) +#define MPMC_DYNAMIC_RASCAS_3 (*(volatile uint32_t*)(MPMC_BASE+0x164)) + +#define MPMC_PERIPH_ID2 (*(volatile uint32_t*)(MPMC_BASE+0xFE8)) /* VIC controller (PL190) registers */ -#define VIC_IRQ_STATUS (*(volatile unsigned long*)(VIC_BASE+0x00)) -#define VIC_FIQ_STATUS (*(volatile unsigned long*)(VIC_BASE+0x04)) -#define VIC_RAW_INTR (*(volatile unsigned long*)(VIC_BASE+0x08)) -#define VIC_INT_SELECT (*(volatile unsigned long*)(VIC_BASE+0x0C)) -#define VIC_INT_ENABLE (*(volatile unsigned long*)(VIC_BASE+0x10)) -#define VIC_INT_EN_CLEAR (*(volatile unsigned long*)(VIC_BASE+0x14)) -#define VIC_SOFT_INT (*(volatile unsigned long*)(VIC_BASE+0x18)) -#define VIC_SOFT_INT_CLEAR (*(volatile unsigned long*)(VIC_BASE+0x1C)) -#define VIC_PROTECTION (*(volatile unsigned long*)(VIC_BASE+0x20)) +#define VIC_IRQ_STATUS (*(volatile uint32_t*)(VIC_BASE+0x00)) +#define VIC_FIQ_STATUS (*(volatile uint32_t*)(VIC_BASE+0x04)) +#define VIC_RAW_INTR (*(volatile uint32_t*)(VIC_BASE+0x08)) +#define VIC_INT_SELECT (*(volatile uint32_t*)(VIC_BASE+0x0C)) +#define VIC_INT_ENABLE (*(volatile uint32_t*)(VIC_BASE+0x10)) +#define VIC_INT_EN_CLEAR (*(volatile uint32_t*)(VIC_BASE+0x14)) +#define VIC_SOFT_INT (*(volatile uint32_t*)(VIC_BASE+0x18)) +#define VIC_SOFT_INT_CLEAR (*(volatile uint32_t*)(VIC_BASE+0x1C)) +#define VIC_PROTECTION (*(volatile uint32_t*)(VIC_BASE+0x20)) #define VIC_VECT_ADDR ((void (* volatile *) (void)) (VIC_BASE+0x30)) #define VIC_DEF_VECT_ADDR ((void (* volatile *) (void)) (VIC_BASE+0x34)) #define VIC_VECT_ADDRS ((void (* volatile *) (void)) (VIC_BASE+0x100)) -#define VIC_VECT_CNTLS ((volatile unsigned long*)(VIC_BASE+0x200)) +#define VIC_VECT_CNTLS ((volatile uint32_t*)(VIC_BASE+0x200)) /* Interrupt sources (for vectors setup) */ #define INT_SRC_WATCHDOG 0 @@ -506,26 +510,26 @@ CE lines /* I2SOUT registers */ -#define I2SOUT_CONTROL (*(volatile unsigned char*)(I2SOUT_BASE+0x00)) -#define I2SOUT_MASK (*(volatile unsigned char*)(I2SOUT_BASE+0x04)) -#define I2SOUT_RAW_STATUS (*(volatile unsigned char*)(I2SOUT_BASE+0x08)) -#define I2SOUT_STATUS (*(volatile unsigned char*)(I2SOUT_BASE+0x0C)) -#define I2SOUT_CLEAR (*(volatile unsigned char*)(I2SOUT_BASE+0x10)) -#define I2SOUT_DATA (volatile unsigned long*)(I2SOUT_BASE+0x14) +#define I2SOUT_CONTROL (*(volatile uint8_t*)(I2SOUT_BASE+0x00)) +#define I2SOUT_MASK (*(volatile uint8_t*)(I2SOUT_BASE+0x04)) +#define I2SOUT_RAW_STATUS (*(volatile uint8_t*)(I2SOUT_BASE+0x08)) +#define I2SOUT_STATUS (*(volatile uint8_t*)(I2SOUT_BASE+0x0C)) +#define I2SOUT_CLEAR (*(volatile uint8_t*)(I2SOUT_BASE+0x10)) +#define I2SOUT_DATA (volatile uint32_t*)(I2SOUT_BASE+0x14) /* SSP registers (PrimeCell PL022) */ -#define SSP_CR0 (*(volatile unsigned short*)(SSP_BASE+0x00)) -#define SSP_CR1 (*(volatile unsigned char*)(SSP_BASE+0x04)) -#define SSP_DATA (*(volatile unsigned short*)(SSP_BASE+0x08)) -#define SSP_SR (*(volatile unsigned char*)(SSP_BASE+0x0C)) -#define SSP_CPSR (*(volatile unsigned char*)(SSP_BASE+0x10)) -#define SSP_IMSC (*(volatile unsigned char*)(SSP_BASE+0x14)) -#define SSP_IRS (*(volatile unsigned char*)(SSP_BASE+0x18)) -#define SSP_MIS (*(volatile unsigned char*)(SSP_BASE+0x1C)) -#define SSP_ICR (*(volatile unsigned char*)(SSP_BASE+0x20)) -#define SSP_DMACR (*(volatile unsigned char*)(SSP_BASE+0x24)) +#define SSP_CR0 (*(volatile uint16_t*)(SSP_BASE+0x00)) +#define SSP_CR1 (*(volatile uint8_t*)(SSP_BASE+0x04)) +#define SSP_DATA (*(volatile uint16_t*)(SSP_BASE+0x08)) +#define SSP_SR (*(volatile uint8_t*)(SSP_BASE+0x0C)) +#define SSP_CPSR (*(volatile uint8_t*)(SSP_BASE+0x10)) +#define SSP_IMSC (*(volatile uint8_t*)(SSP_BASE+0x14)) +#define SSP_IRS (*(volatile uint8_t*)(SSP_BASE+0x18)) +#define SSP_MIS (*(volatile uint8_t*)(SSP_BASE+0x1C)) +#define SSP_ICR (*(volatile uint8_t*)(SSP_BASE+0x20)) +#define SSP_DMACR (*(volatile uint8_t*)(SSP_BASE+0x24)) /* PCM addresses for obtaining buffers will be what DMA is using (physical) */ #define HAVE_PCM_DMA_ADDRESS @@ -539,13 +543,13 @@ CE lines /* I2SIN registers */ -#define I2SIN_CONTROL (*(volatile unsigned long*)(I2SIN_BASE+0x00)) -#define I2SIN_MASK (*(volatile unsigned char*)(I2SIN_BASE+0x04)) -#define I2SIN_RAW_STATUS (*(volatile unsigned char*)(I2SIN_BASE+0x08)) -#define I2SIN_STATUS (*(volatile unsigned char*)(I2SIN_BASE+0x0C)) -#define I2SIN_CLEAR (*(volatile unsigned char*)(I2SIN_BASE+0x10)) -#define I2SIN_DATA (volatile unsigned long*)(I2SIN_BASE+0x14) -#define I2SIN_SPDIF_STATUS (*(volatile unsigned long*)(I2SIN_BASE+0x18)) +#define I2SIN_CONTROL (*(volatile uint32_t*)(I2SIN_BASE+0x00)) +#define I2SIN_MASK (*(volatile uint8_t*)(I2SIN_BASE+0x04)) +#define I2SIN_RAW_STATUS (*(volatile uint8_t*)(I2SIN_BASE+0x08)) +#define I2SIN_STATUS (*(volatile uint8_t*)(I2SIN_BASE+0x0C)) +#define I2SIN_CLEAR (*(volatile uint8_t*)(I2SIN_BASE+0x10)) +#define I2SIN_DATA (volatile uint32_t*)(I2SIN_BASE+0x14) +#define I2SIN_SPDIF_STATUS (*(volatile uint32_t*)(I2SIN_BASE+0x18)) /* I2SIN_MASK */ diff --git a/firmware/export/as3525v2.h b/firmware/export/as3525v2.h index f68a07a2fb..428ef4a81e 100644 --- a/firmware/export/as3525v2.h +++ b/firmware/export/as3525v2.h @@ -34,13 +34,13 @@ #undef IRAM_SIZE #define IRAM_SIZE 0x100000 -#define CGU_SDSLOT (*(volatile unsigned long *)(CGU_BASE + 0x3C)) +#define CGU_SDSLOT (*(volatile uint32_t*)(CGU_BASE + 0x3C)) #undef USB_NUM_ENDPOINTS /* 7 available EPs (0b00000000010101010000000000101011), 6 used */ #define USB_NUM_ENDPOINTS 6 -#define CCU_USB (*(volatile unsigned long *)(CCU_BASE + 0x20)) +#define CCU_USB (*(volatile uint32_t*)(CCU_BASE + 0x20)) #undef USB_DEVBSS_ATTR #define USB_DEVBSS_ATTR __attribute__((aligned(32))) diff --git a/firmware/export/imx31l.h b/firmware/export/imx31l.h index ca4ab0c019..762e9bb2d5 100644 --- a/firmware/export/imx31l.h +++ b/firmware/export/imx31l.h @@ -21,17 +21,21 @@ #ifndef __IMX31L_H__ #define __IMX31L_H__ +#if !defined(__ASSEMBLER__) +#include <stdint.h> +#endif + /* Most(if not all) of these defines are copied from Nand-Boot v4 provided w/ the Imx31 Linux Bsp*/ -#define REG8_PTR_T volatile unsigned char * -#define REG16_PTR_T volatile unsigned short * -#define REG32_PTR_T volatile unsigned long * +#define REG8_PTR_T volatile uint8_t * +#define REG16_PTR_T volatile uint16_t * +#define REG32_PTR_T volatile uint32_t * /* Place in the section with the framebuffer */ #define TTB_BASE_ADDR (CSD0_BASE_ADDR + (MEMORYSIZE*0x100000) - TTB_SIZE) #define TTB_SIZE (0x4000) #define IRAM_SIZE (0x4000) -#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) +#define TTB_BASE ((uint32_t *)TTB_BASE_ADDR) #define FRAME_SIZE (240*320*2) /* Rockbox framebuffer address, not retail OS */ #define FRAME_PHYS_ADDR (TTB_BASE_ADDR - FRAME_SIZE) diff --git a/firmware/export/pl081.h b/firmware/export/pl081.h index 3a75104ab6..258850b3e8 100644 --- a/firmware/export/pl081.h +++ b/firmware/export/pl081.h @@ -24,33 +24,33 @@ /* ARM PrimeCell PL081 Single Master DMA controller */ -#define DMAC_INT_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x000)) -#define DMAC_INT_TC_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x004)) -#define DMAC_INT_TC_CLEAR (*(volatile unsigned long*)(DMAC_BASE+0x008)) -#define DMAC_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x00C)) -#define DMAC_INT_ERR_CLEAR (*(volatile unsigned long*)(DMAC_BASE+0x010)) -#define DMAC_RAW_INT_TC_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x014)) -#define DMAC_RAW_INT_ERROR_STATUS (*(volatile unsigned long*)(DMAC_BASE+0x018)) -#define DMAC_ENBLD_CHANS (*(volatile unsigned long*)(DMAC_BASE+0x01C)) -#define DMAC_SOFT_B_REQ (*(volatile unsigned long*)(DMAC_BASE+0x020)) -#define DMAC_SOFT_S_REQ (*(volatile unsigned long*)(DMAC_BASE+0x024)) -#define DMAC_SOFT_LB_REQ (*(volatile unsigned long*)(DMAC_BASE+0x028)) -#define DMAC_SOFT_LS_REQ (*(volatile unsigned long*)(DMAC_BASE+0x02C)) -#define DMAC_CONFIGURATION (*(volatile unsigned long*)(DMAC_BASE+0x030)) -#define DMAC_SYNC (*(volatile unsigned long*)(DMAC_BASE+0x034)) +#define DMAC_INT_STATUS (*(volatile uint32_t*)(DMAC_BASE+0x000)) +#define DMAC_INT_TC_STATUS (*(volatile uint32_t*)(DMAC_BASE+0x004)) +#define DMAC_INT_TC_CLEAR (*(volatile uint32_t*)(DMAC_BASE+0x008)) +#define DMAC_INT_ERROR_STATUS (*(volatile uint32_t*)(DMAC_BASE+0x00C)) +#define DMAC_INT_ERR_CLEAR (*(volatile uint32_t*)(DMAC_BASE+0x010)) +#define DMAC_RAW_INT_TC_STATUS (*(volatile uint32_t*)(DMAC_BASE+0x014)) +#define DMAC_RAW_INT_ERROR_STATUS (*(volatile uint32_t*)(DMAC_BASE+0x018)) +#define DMAC_ENBLD_CHANS (*(volatile uint32_t*)(DMAC_BASE+0x01C)) +#define DMAC_SOFT_B_REQ (*(volatile uint32_t*)(DMAC_BASE+0x020)) +#define DMAC_SOFT_S_REQ (*(volatile uint32_t*)(DMAC_BASE+0x024)) +#define DMAC_SOFT_LB_REQ (*(volatile uint32_t*)(DMAC_BASE+0x028)) +#define DMAC_SOFT_LS_REQ (*(volatile uint32_t*)(DMAC_BASE+0x02C)) +#define DMAC_CONFIGURATION (*(volatile uint32_t*)(DMAC_BASE+0x030)) +#define DMAC_SYNC (*(volatile uint32_t*)(DMAC_BASE+0x034)) /* Channel registers (0 & 1) */ -#define DMAC_CH_SRC_ADDR(c) (*(volatile unsigned long*)(DMAC_BASE+0x100+(0x20*c))) -#define DMAC_CH_DST_ADDR(c) (*(volatile unsigned long*)(DMAC_BASE+0x104+(0x20*c))) -#define DMAC_CH_LLI(c) (*(volatile unsigned long*)(DMAC_BASE+0x108+(0x20*c))) -#define DMAC_CH_CONTROL(c) (*(volatile unsigned long*)(DMAC_BASE+0x10C+(0x20*c))) -#define DMAC_CH_CONFIGURATION(c) (*(volatile unsigned long*)(DMAC_BASE+0x110+(0x20*c))) +#define DMAC_CH_SRC_ADDR(c) (*(volatile uint32_t*)(DMAC_BASE+0x100+(0x20*c))) +#define DMAC_CH_DST_ADDR(c) (*(volatile uint32_t*)(DMAC_BASE+0x104+(0x20*c))) +#define DMAC_CH_LLI(c) (*(volatile uint32_t*)(DMAC_BASE+0x108+(0x20*c))) +#define DMAC_CH_CONTROL(c) (*(volatile uint32_t*)(DMAC_BASE+0x10C+(0x20*c))) +#define DMAC_CH_CONFIGURATION(c) (*(volatile uint32_t*)(DMAC_BASE+0x110+(0x20*c))) /* Test registers */ -#define DMAC_ITCR (*(volatile unsigned long*)(DMAC_BASE+0x500)) -#define DMAC_ITOP1 (*(volatile unsigned long*)(DMAC_BASE+0x504)) -#define DMAC_ITOP2 (*(volatile unsigned long*)(DMAC_BASE+0x508)) -#define DMAC_ITOP3 (*(volatile unsigned long*)(DMAC_BASE+0x50C)) +#define DMAC_ITCR (*(volatile uint32_t*)(DMAC_BASE+0x500)) +#define DMAC_ITOP1 (*(volatile uint32_t*)(DMAC_BASE+0x504)) +#define DMAC_ITOP2 (*(volatile uint32_t*)(DMAC_BASE+0x508)) +#define DMAC_ITOP3 (*(volatile uint32_t*)(DMAC_BASE+0x50C)) /* Flow controllers */ diff --git a/firmware/export/s3c2440.h b/firmware/export/s3c2440.h index c0dc97aed5..f57dd385d0 100644 --- a/firmware/export/s3c2440.h +++ b/firmware/export/s3c2440.h @@ -30,24 +30,24 @@ #define TTB_BASE_ADDR (0x30000000 + (MEMORYSIZE*1024*1024) - TTB_SIZE) #define LCD_FRAME_ADDR (TTB_BASE_ADDR - LCD_BUFFER_SIZE) -#define TTB_BASE ((unsigned long *)TTB_BASE_ADDR) /* End of memory */ -#define FRAME ((unsigned short *)LCD_FRAME_ADDR) /* Right before TTB */ +#define TTB_BASE ((uint32_t *)TTB_BASE_ADDR) /* End of memory */ +#define FRAME ((unsigned short *)LCD_FRAME_ADDR) /* Right before TTB */ /* Memory Controllers */ -#define BWSCON (*(volatile unsigned long *)0x48000000) /* Bus width & wait status control */ -#define BANKCON0 (*(volatile unsigned long *)0x48000004) /* Boot ROM control */ -#define BANKCON1 (*(volatile unsigned long *)0x48000008) /* BANK1 control */ -#define BANKCON2 (*(volatile unsigned long *)0x4800000C) /* BANK2 control */ -#define BANKCON3 (*(volatile unsigned long *)0x48000010) /* BANK3 control */ -#define BANKCON4 (*(volatile unsigned long *)0x48000014) /* BANK4 control */ -#define BANKCON5 (*(volatile unsigned long *)0x48000018) /* BANK5 control */ -#define BANKCON6 (*(volatile unsigned long *)0x4800001C) /* BANK6 control */ -#define BANKCON7 (*(volatile unsigned long *)0x48000020) /* BANK7 control */ -#define REFRESH (*(volatile unsigned long *)0x48000024) /* DRAM/SDRAM refresh control */ -#define BANKSIZE (*(volatile unsigned long *)0x48000028) /* Flexible bank size */ -#define MRSRB6 (*(volatile unsigned long *)0x4800002C) /* Mode register set for SDRAM BANK6 */ -#define MRSRB7 (*(volatile unsigned long *)0x48000030) /* Mode register set for SDRAM BANK7 */ +#define BWSCON (*(volatile uint32_t *)0x48000000) /* Bus width & wait status control */ +#define BANKCON0 (*(volatile uint32_t *)0x48000004) /* Boot ROM control */ +#define BANKCON1 (*(volatile uint32_t *)0x48000008) /* BANK1 control */ +#define BANKCON2 (*(volatile uint32_t *)0x4800000C) /* BANK2 control */ +#define BANKCON3 (*(volatile uint32_t *)0x48000010) /* BANK3 control */ +#define BANKCON4 (*(volatile uint32_t *)0x48000014) /* BANK4 control */ +#define BANKCON5 (*(volatile uint32_t *)0x48000018) /* BANK5 control */ +#define BANKCON6 (*(volatile uint32_t *)0x4800001C) /* BANK6 control */ +#define BANKCON7 (*(volatile uint32_t *)0x48000020) /* BANK7 control */ +#define REFRESH (*(volatile uint32_t *)0x48000024) /* DRAM/SDRAM refresh control */ +#define BANKSIZE (*(volatile uint32_t *)0x48000028) /* Flexible bank size */ +#define MRSRB6 (*(volatile uint32_t *)0x4800002C) /* Mode register set for SDRAM BANK6 */ +#define MRSRB7 (*(volatile uint32_t *)0x48000030) /* Mode register set for SDRAM BANK7 */ /* USB Host Controller */ @@ -55,14 +55,14 @@ /* Interrupt Controller */ -#define SRCPND (*(volatile unsigned long *)0x4A000000) /* Interrupt request status */ -#define INTMOD (*(volatile unsigned long *)0x4A000004) /* Interrupt mode control */ -#define INTMSK (*(volatile unsigned long *)0x4A000008) /* Interrupt mask control */ -#define PRIORITY (*(volatile unsigned long *)0x4A00000C) /* IRQ priority control */ -#define INTPND (*(volatile unsigned long *)0x4A000010) /* Interrupt request status */ -#define INTOFFSET (*(volatile unsigned long *)0x4A000014) /* Interrupt request source offset */ -#define SUBSRCPND (*(volatile unsigned long *)0x4A000018) /* Sub source pending */ -#define INTSUBMSK (*(volatile unsigned long *)0x4A00001C) /* Interrupt sub mask */ +#define SRCPND (*(volatile uint32_t *)0x4A000000) /* Interrupt request status */ +#define INTMOD (*(volatile uint32_t *)0x4A000004) /* Interrupt mode control */ +#define INTMSK (*(volatile uint32_t *)0x4A000008) /* Interrupt mask control */ +#define PRIORITY (*(volatile uint32_t *)0x4A00000C) /* IRQ priority control */ +#define INTPND (*(volatile uint32_t *)0x4A000010) /* Interrupt request status */ +#define INTOFFSET (*(volatile uint32_t *)0x4A000014) /* Interrupt request source offset */ +#define SUBSRCPND (*(volatile uint32_t *)0x4A000018) /* Sub source pending */ +#define INTSUBMSK (*(volatile uint32_t *)0x4A00001C) /* Interrupt sub mask */ /* Interrupt indexes - INTOFFSET - IRQ mode only */ /* Arbiter 5 => Arbiter 6 Req 5 */ @@ -146,42 +146,42 @@ /* DMA */ -#define DISRC0 (*(volatile unsigned long *)0x4B000000) /* DMA 0 initial source */ -#define DISRCC0 (*(volatile unsigned long *)0x4B000004) /* DMA 0 initial source control */ -#define DIDST0 (*(volatile unsigned long *)0x4B000008) /* DMA 0 initial destination */ -#define DIDSTC0 (*(volatile unsigned long *)0x4B00000C) /* DMA 0 initial destination control */ -#define DCON0 (*(volatile unsigned long *)0x4B000010) /* DMA 0 control */ -#define DSTAT0 (*(volatile unsigned long *)0x4B000014) /* DMA 0 count */ -#define DCSRC0 (*(volatile unsigned long *)0x4B000018) /* DMA 0 current source */ -#define DCDST0 (*(volatile unsigned long *)0x4B00001C) /* DMA 0 current destination */ -#define DMASKTRIG0 (*(volatile unsigned long *)0x4B000020) /* DMA 0 mask trigger */ -#define DISRC1 (*(volatile unsigned long *)0x4B000040) /* DMA 1 initial source */ -#define DISRCC1 (*(volatile unsigned long *)0x4B000044) /* DMA 1 initial source control */ -#define DIDST1 (*(volatile unsigned long *)0x4B000048) /* DMA 1 initial destination */ -#define DIDSTC1 (*(volatile unsigned long *)0x4B00004C) /* DMA 1 initial destination control */ -#define DCON1 (*(volatile unsigned long *)0x4B000050) /* DMA 1 control */ -#define DSTAT1 (*(volatile unsigned long *)0x4B000054) /* DMA 1 count */ -#define DCSRC1 (*(volatile unsigned long *)0x4B000058) /* DMA 1 current source */ -#define DCDST1 (*(volatile unsigned long *)0x4B00005C) /* DMA 1 current destination */ -#define DMASKTRIG1 (*(volatile unsigned long *)0x4B000060) /* DMA 1 mask trigger */ -#define DISRC2 (*(volatile unsigned long *)0x4B000080) /* DMA 2 initial source */ -#define DISRCC2 (*(volatile unsigned long *)0x4B000084) /* DMA 2 initial source control */ -#define DIDST2 (*(volatile unsigned long *)0x4B000088) /* DMA 2 initial destination */ -#define DIDSTC2 (*(volatile unsigned long *)0x4B00008C) /* DMA 2 initial destination control */ -#define DCON2 (*(volatile unsigned long *)0x4B000090) /* DMA 2 control */ -#define DSTAT2 (*(volatile unsigned long *)0x4B000094) /* DMA 2 count */ -#define DCSRC2 (*(volatile unsigned long *)0x4B000098) /* DMA 2 current source */ -#define DCDST2 (*(volatile unsigned long *)0x4B00009C) /* DMA 2 current destination */ -#define DMASKTRIG2 (*(volatile unsigned long *)0x4B0000A0) /* DMA 2 mask trigger */ -#define DISRC3 (*(volatile unsigned long *)0x4B0000C0) /* DMA 3 initial source */ -#define DISRCC3 (*(volatile unsigned long *)0x4B0000C4) /* DMA 3 initial source control */ -#define DIDST3 (*(volatile unsigned long *)0x4B0000C8) /* DMA 3 initial destination */ -#define DIDSTC3 (*(volatile unsigned long *)0x4B0000CC) /* DMA 3 initial destination control */ -#define DCON3 (*(volatile unsigned long *)0x4B0000D0) /* DMA 3 control */ -#define DSTAT3 (*(volatile unsigned long *)0x4B0000D4) /* DMA 3 count */ -#define DCSRC3 (*(volatile unsigned long *)0x4B0000D8) /* DMA 3 current source */ -#define DCDST3 (*(volatile unsigned long *)0x4B0000DC) /* DMA 3 current destination */ -#define DMASKTRIG3 (*(volatile unsigned long *)0x4B0000E0) /* DMA 3 mask trigger */ +#define DISRC0 (*(volatile uint32_t *)0x4B000000) /* DMA 0 initial source */ +#define DISRCC0 (*(volatile uint32_t *)0x4B000004) /* DMA 0 initial source control */ +#define DIDST0 (*(volatile uint32_t *)0x4B000008) /* DMA 0 initial destination */ +#define DIDSTC0 (*(volatile uint32_t *)0x4B00000C) /* DMA 0 initial destination control */ +#define DCON0 (*(volatile uint32_t *)0x4B000010) /* DMA 0 control */ +#define DSTAT0 (*(volatile uint32_t *)0x4B000014) /* DMA 0 count */ +#define DCSRC0 (*(volatile uint32_t *)0x4B000018) /* DMA 0 current source */ +#define DCDST0 (*(volatile uint32_t *)0x4B00001C) /* DMA 0 current destination */ +#define DMASKTRIG0 (*(volatile uint32_t *)0x4B000020) /* DMA 0 mask trigger */ +#define DISRC1 (*(volatile uint32_t *)0x4B000040) /* DMA 1 initial source */ +#define DISRCC1 (*(volatile uint32_t *)0x4B000044) /* DMA 1 initial source control */ +#define DIDST1 (*(volatile uint32_t *)0x4B000048) /* DMA 1 initial destination */ +#define DIDSTC1 (*(volatile uint32_t *)0x4B00004C) /* DMA 1 initial destination control */ +#define DCON1 (*(volatile uint32_t *)0x4B000050) /* DMA 1 control */ +#define DSTAT1 (*(volatile uint32_t *)0x4B000054) /* DMA 1 count */ +#define DCSRC1 (*(volatile uint32_t *)0x4B000058) /* DMA 1 current source */ +#define DCDST1 (*(volatile uint32_t *)0x4B00005C) /* DMA 1 current destination */ +#define DMASKTRIG1 (*(volatile uint32_t *)0x4B000060) /* DMA 1 mask trigger */ +#define DISRC2 (*(volatile uint32_t *)0x4B000080) /* DMA 2 initial source */ +#define DISRCC2 (*(volatile uint32_t *)0x4B000084) /* DMA 2 initial source control */ +#define DIDST2 (*(volatile uint32_t *)0x4B000088) /* DMA 2 initial destination */ +#define DIDSTC2 (*(volatile uint32_t *)0x4B00008C) /* DMA 2 initial destination control */ +#define DCON2 (*(volatile uint32_t *)0x4B000090) /* DMA 2 control */ +#define DSTAT2 (*(volatile uint32_t *)0x4B000094) /* DMA 2 count */ +#define DCSRC2 (*(volatile uint32_t *)0x4B000098) /* DMA 2 current source */ +#define DCDST2 (*(volatile uint32_t *)0x4B00009C) /* DMA 2 current destination */ +#define DMASKTRIG2 (*(volatile uint32_t *)0x4B0000A0) /* DMA 2 mask trigger */ +#define DISRC3 (*(volatile uint32_t *)0x4B0000C0) /* DMA 3 initial source */ +#define DISRCC3 (*(volatile uint32_t *)0x4B0000C4) /* DMA 3 initial source control */ +#define DIDST3 (*(volatile uint32_t *)0x4B0000C8) /* DMA 3 initial destination */ +#define DIDSTC3 (*(volatile uint32_t *)0x4B0000CC) /* DMA 3 initial destination control */ +#define DCON3 (*(volatile uint32_t *)0x4B0000D0) /* DMA 3 control */ +#define DSTAT3 (*(volatile uint32_t *)0x4B0000D4) /* DMA 3 count */ +#define DCSRC3 (*(volatile uint32_t *)0x4B0000D8) /* DMA 3 current source */ +#define DCDST3 (*(volatile uint32_t *)0x4B0000DC) /* DMA 3 current destination */ +#define DMASKTRIG3 (*(volatile uint32_t *)0x4B0000E0) /* DMA 3 mask trigger */ #define DISRCC_LOC_AHB (0 << 1) #define DISRCC_LOC_APB (1 << 1) @@ -255,146 +255,146 @@ /* Clock & Power Management */ -#define LOCKTIME (*(volatile unsigned long *)0x4C000000) /* PLL lock time counter */ -#define MPLLCON (*(volatile unsigned long *)0x4C000004) /* MPLL control */ -#define UPLLCON (*(volatile unsigned long *)0x4C000008) /* UPLL control */ -#define CLKCON (*(volatile unsigned long *)0x4C00000C) /* Clock generator control */ -#define CLKSLOW (*(volatile unsigned long *)0x4C000010) /* Slow clock control */ -#define CLKDIVN (*(volatile unsigned long *)0x4C000014) /* Clock divider control */ -#define CAMDIVN (*(volatile unsigned long *)0x4C000018) /* Camera clock divider control */ +#define LOCKTIME (*(volatile uint32_t *)0x4C000000) /* PLL lock time counter */ +#define MPLLCON (*(volatile uint32_t *)0x4C000004) /* MPLL control */ +#define UPLLCON (*(volatile uint32_t *)0x4C000008) /* UPLL control */ +#define CLKCON (*(volatile uint32_t *)0x4C00000C) /* Clock generator control */ +#define CLKSLOW (*(volatile uint32_t *)0x4C000010) /* Slow clock control */ +#define CLKDIVN (*(volatile uint32_t *)0x4C000014) /* Clock divider control */ +#define CAMDIVN (*(volatile uint32_t *)0x4C000018) /* Camera clock divider control */ /* LCD Controller */ -#define LCDCON1 (*(volatile unsigned long *)0x4D000000) /* LCD control 1 */ -#define LCDCON2 (*(volatile unsigned long *)0x4D000004) /* LCD control 2 */ -#define LCDCON3 (*(volatile unsigned long *)0x4D000008) /* LCD control 3 */ -#define LCDCON4 (*(volatile unsigned long *)0x4D00000C) /* LCD control 4 */ -#define LCDCON5 (*(volatile unsigned long *)0x4D000010) /* LCD control 5 */ -#define LCDSADDR1 (*(volatile unsigned long *)0x4D000014) /* STN/TFT: frame buffer start address 1 */ -#define LCDSADDR2 (*(volatile unsigned long *)0x4D000018) /* STN/TFT: frame buffer start address 2 */ -#define LCDSADDR3 (*(volatile unsigned long *)0x4D00001C) /* STN/TFT: virtual screen address set */ -#define REDLUT (*(volatile unsigned long *)0x4D000020) /* STN: red lookup table */ -#define GREENLUT (*(volatile unsigned long *)0x4D000024) /* STN: green lookup table */ -#define BLUELUT (*(volatile unsigned long *)0x4D000028) /* STN: blue lookup table */ -#define DITHMODE (*(volatile unsigned long *)0x4D00004C) /* STN: dithering mode */ -#define TPAL (*(volatile unsigned long *)0x4D000050) /* TFT: temporary palette */ -#define LCDINTPND (*(volatile unsigned long *)0x4D000054) /* LCD interrupt pending */ -#define LCDSRCPND (*(volatile unsigned long *)0x4D000058) /* LCD interrupt source */ -#define LCDINTMSK (*(volatile unsigned long *)0x4D00005C) /* LCD interrupt mask */ -#define TCONSEL (*(volatile unsigned long *)0x4D000060) /* TCON(LPC3600/LCC3600) control */ +#define LCDCON1 (*(volatile uint32_t *)0x4D000000) /* LCD control 1 */ +#define LCDCON2 (*(volatile uint32_t *)0x4D000004) /* LCD control 2 */ +#define LCDCON3 (*(volatile uint32_t *)0x4D000008) /* LCD control 3 */ +#define LCDCON4 (*(volatile uint32_t *)0x4D00000C) /* LCD control 4 */ +#define LCDCON5 (*(volatile uint32_t *)0x4D000010) /* LCD control 5 */ +#define LCDSADDR1 (*(volatile uint32_t *)0x4D000014) /* STN/TFT: frame buffer start address 1 */ +#define LCDSADDR2 (*(volatile uint32_t *)0x4D000018) /* STN/TFT: frame buffer start address 2 */ +#define LCDSADDR3 (*(volatile uint32_t *)0x4D00001C) /* STN/TFT: virtual screen address set */ +#define REDLUT (*(volatile uint32_t *)0x4D000020) /* STN: red lookup table */ +#define GREENLUT (*(volatile uint32_t *)0x4D000024) /* STN: green lookup table */ +#define BLUELUT (*(volatile uint32_t *)0x4D000028) /* STN: blue lookup table */ +#define DITHMODE (*(volatile uint32_t *)0x4D00004C) /* STN: dithering mode */ +#define TPAL (*(volatile uint32_t *)0x4D000050) /* TFT: temporary palette */ +#define LCDINTPND (*(volatile uint32_t *)0x4D000054) /* LCD interrupt pending */ +#define LCDSRCPND (*(volatile uint32_t *)0x4D000058) /* LCD interrupt source */ +#define LCDINTMSK (*(volatile uint32_t *)0x4D00005C) /* LCD interrupt mask */ +#define TCONSEL (*(volatile uint32_t *)0x4D000060) /* TCON(LPC3600/LCC3600) control */ /* NAND Flash */ -#define NFCONF (*(volatile unsigned long *)0x4E000000) /* NAND flash configuration */ -#define NFCONT (*(volatile unsigned long *)0x4E000004) /* NAND flash control */ -#define NFCMD (*(volatile unsigned long *)0x4E000008) /* NAND flash command */ -#define NFADDR (*(volatile unsigned long *)0x4E00000C) /* NAND flash address */ -#define NFDATA (*(volatile unsigned long *)0x4E000010) /* NAND flash data */ -#define NFMECC0 (*(volatile unsigned long *)0x4E000014) /* NAND flash main area ECC0/1 */ -#define NFMECC1 (*(volatile unsigned long *)0x4E000018) /* NAND flash main area ECC2/3 */ -#define NFSECC (*(volatile unsigned long *)0x4E00001C) /* NAND flash spare area ECC */ -#define NFSTAT (*(volatile unsigned long *)0x4E000020) /* NAND flash operation status */ -#define NFESTAT0 (*(volatile unsigned long *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */ -#define NFESTAT1 (*(volatile unsigned long *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */ -#define NFMECCSTAT0 (*(volatile unsigned long *)0x4E00002C) /* NAND flash main area ECC0 status */ -#define NFMECCSTAT1 (*(volatile unsigned long *)0x4E000030) /* NAND flash main area ECC1 status */ -#define NFSECCSTAT (*(volatile unsigned long *)0x4E000034) /* NAND flash spare area ECC status */ -#define NFSBLK (*(volatile unsigned long *)0x4E000038) /* NAND flash start block address */ -#define NFEBLK (*(volatile unsigned long *)0x4E00003C) /* NAND flash end block address */ +#define NFCONF (*(volatile uint32_t *)0x4E000000) /* NAND flash configuration */ +#define NFCONT (*(volatile uint32_t *)0x4E000004) /* NAND flash control */ +#define NFCMD (*(volatile uint32_t *)0x4E000008) /* NAND flash command */ +#define NFADDR (*(volatile uint32_t *)0x4E00000C) /* NAND flash address */ +#define NFDATA (*(volatile uint32_t *)0x4E000010) /* NAND flash data */ +#define NFMECC0 (*(volatile uint32_t *)0x4E000014) /* NAND flash main area ECC0/1 */ +#define NFMECC1 (*(volatile uint32_t *)0x4E000018) /* NAND flash main area ECC2/3 */ +#define NFSECC (*(volatile uint32_t *)0x4E00001C) /* NAND flash spare area ECC */ +#define NFSTAT (*(volatile uint32_t *)0x4E000020) /* NAND flash operation status */ +#define NFESTAT0 (*(volatile uint32_t *)0x4E000024) /* NAND flash ECC status for I/O[7:0] */ +#define NFESTAT1 (*(volatile uint32_t *)0x4E000028) /* NAND flash ECC status for I/O[15:8] */ +#define NFMECCSTAT0 (*(volatile uint32_t *)0x4E00002C) /* NAND flash main area ECC0 status */ +#define NFMECCSTAT1 (*(volatile uint32_t *)0x4E000030) /* NAND flash main area ECC1 status */ +#define NFSECCSTAT (*(volatile uint32_t *)0x4E000034) /* NAND flash spare area ECC status */ +#define NFSBLK (*(volatile uint32_t *)0x4E000038) /* NAND flash start block address */ +#define NFEBLK (*(volatile uint32_t *)0x4E00003C) /* NAND flash end block address */ /* Camera Interface */ -#define CISRCFMT (*(volatile unsigned long *)0x4F000000) /* Input source format */ -#define CIWDOFST (*(volatile unsigned long *)0x4F000004) /* Window offset register */ -#define CIGCTRL (*(volatile unsigned long *)0x4F000008) /* Global control register */ -#define CICOYSA1 (*(volatile unsigned long *)0x4F000018) /* Y 1st frame start address for codec DMA */ -#define CICOYSA2 (*(volatile unsigned long *)0x4F00001C) /* Y 2nd frame start address for codec DMA */ -#define CICOYSA3 (*(volatile unsigned long *)0x4F000020) /* Y 3nd frame start address for codec DMA */ -#define CICOYSA4 (*(volatile unsigned long *)0x4F000024) /* Y 4th frame start address for codec DMA */ -#define CICOCBSA1 (*(volatile unsigned long *)0x4F000028) /* Cb 1st frame start address for codec DMA */ -#define CICOCBSA2 (*(volatile unsigned long *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */ -#define CICOCBSA3 (*(volatile unsigned long *)0x4F000030) /* Cb 3nd frame start address for codec DMA */ -#define CICOCBSA4 (*(volatile unsigned long *)0x4F000034) /* Cb 4th frame start address for codec DMA */ -#define CICOCRSA1 (*(volatile unsigned long *)0x4F000038) /* Cr 1st frame start address for codec DMA */ -#define CICOCRSA2 (*(volatile unsigned long *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */ -#define CICOCRSA3 (*(volatile unsigned long *)0x4F000040) /* Cr 3nd frame start address for codec DMA */ -#define CICOCRSA4 (*(volatile unsigned long *)0x4F000044) /* Cr 4th frame start address for codec DMA */ -#define CICOTRGFMT (*(volatile unsigned long *)0x4F000048) /* Target image format of codec DMA */ -#define CICOCTRL (*(volatile unsigned long *)0x4F00004C) +#define CISRCFMT (*(volatile uint32_t *)0x4F000000) /* Input source format */ +#define CIWDOFST (*(volatile uint32_t *)0x4F000004) /* Window offset register */ +#define CIGCTRL (*(volatile uint32_t *)0x4F000008) /* Global control register */ +#define CICOYSA1 (*(volatile uint32_t *)0x4F000018) /* Y 1st frame start address for codec DMA */ +#define CICOYSA2 (*(volatile uint32_t *)0x4F00001C) /* Y 2nd frame start address for codec DMA */ +#define CICOYSA3 (*(volatile uint32_t *)0x4F000020) /* Y 3nd frame start address for codec DMA */ +#define CICOYSA4 (*(volatile uint32_t *)0x4F000024) /* Y 4th frame start address for codec DMA */ +#define CICOCBSA1 (*(volatile uint32_t *)0x4F000028) /* Cb 1st frame start address for codec DMA */ +#define CICOCBSA2 (*(volatile uint32_t *)0x4F00002C) /* Cb 2nd frame start address for codec DMA */ +#define CICOCBSA3 (*(volatile uint32_t *)0x4F000030) /* Cb 3nd frame start address for codec DMA */ +#define CICOCBSA4 (*(volatile uint32_t *)0x4F000034) /* Cb 4th frame start address for codec DMA */ +#define CICOCRSA1 (*(volatile uint32_t *)0x4F000038) /* Cr 1st frame start address for codec DMA */ +#define CICOCRSA2 (*(volatile uint32_t *)0x4F00003C) /* Cr 2nd frame start address for codec DMA */ +#define CICOCRSA3 (*(volatile uint32_t *)0x4F000040) /* Cr 3nd frame start address for codec DMA */ +#define CICOCRSA4 (*(volatile uint32_t *)0x4F000044) /* Cr 4th frame start address for codec DMA */ +#define CICOTRGFMT (*(volatile uint32_t *)0x4F000048) /* Target image format of codec DMA */ +#define CICOCTRL (*(volatile uint32_t *)0x4F00004C) /* Codec DMA control related */ -#define CICOSCPRERATIO (*(volatile unsigned long *)0x4F000050) /* Codec pre-scaler ratio control */ -#define CICOSCPREDST (*(volatile unsigned long *)0x4F000054) /* Codec pre-scaler destination format */ -#define CICOSCCTRL (*(volatile unsigned long *)0x4F000058) /* Codec main-scaler control */ -#define CICOTAREA (*(volatile unsigned long *)0x4F00005C) /* Codec scaler target area */ -#define CICOSTATUS (*(volatile unsigned long *)0x4F000064) /* Codec path status */ -#define CIPRCLRSA1 (*(volatile unsigned long *)0x4F00006C) /* RGB 1st frame start address for preview DMA */ -#define CIPRCLRSA2 (*(volatile unsigned long *)0x4F000070) /* RGB 2nd frame start address for preview DMA */ -#define CIPRCLRSA3 (*(volatile unsigned long *)0x4F000074) /* RGB 3nd frame start address for preview DMA */ -#define CIPRCLRSA4 (*(volatile unsigned long *)0x4F000078) /* RGB 4th frame start address for preview DMA */ -#define CIPRTRGFMT (*(volatile unsigned long *)0x4F00007C) /* Target image format of preview DMA */ -#define CIPRCTRL (*(volatile unsigned long *)0x4F000080) /* Preview DMA control related */ -#define CIPRSCPRERATIO (*(volatile unsigned long *)0x4F000084) /* Preview pre-scaler ratio control */ -#define CIPRSCPREDST (*(volatile unsigned long *)0x4F000088) /* Preview pre-scaler destination format */ -#define CIPRSCCTRL (*(volatile unsigned long *)0x4F00008C) /* Preview main-scaler control */ -#define CIPRTAREA (*(volatile unsigned long *)0x4F000090) /* Preview scaler target area */ -#define CIPRSTATUS (*(volatile unsigned long *)0x4F000098) /* Preview path status */ -#define CIIMGCPT (*(volatile unsigned long *)0x4F0000A0) /* Image capture enable command */ +#define CICOSCPRERATIO (*(volatile uint32_t *)0x4F000050) /* Codec pre-scaler ratio control */ +#define CICOSCPREDST (*(volatile uint32_t *)0x4F000054) /* Codec pre-scaler destination format */ +#define CICOSCCTRL (*(volatile uint32_t *)0x4F000058) /* Codec main-scaler control */ +#define CICOTAREA (*(volatile uint32_t *)0x4F00005C) /* Codec scaler target area */ +#define CICOSTATUS (*(volatile uint32_t *)0x4F000064) /* Codec path status */ +#define CIPRCLRSA1 (*(volatile uint32_t *)0x4F00006C) /* RGB 1st frame start address for preview DMA */ +#define CIPRCLRSA2 (*(volatile uint32_t *)0x4F000070) /* RGB 2nd frame start address for preview DMA */ +#define CIPRCLRSA3 (*(volatile uint32_t *)0x4F000074) /* RGB 3nd frame start address for preview DMA */ +#define CIPRCLRSA4 (*(volatile uint32_t *)0x4F000078) /* RGB 4th frame start address for preview DMA */ +#define CIPRTRGFMT (*(volatile uint32_t *)0x4F00007C) /* Target image format of preview DMA */ +#define CIPRCTRL (*(volatile uint32_t *)0x4F000080) /* Preview DMA control related */ +#define CIPRSCPRERATIO (*(volatile uint32_t *)0x4F000084) /* Preview pre-scaler ratio control */ +#define CIPRSCPREDST (*(volatile uint32_t *)0x4F000088) /* Preview pre-scaler destination format */ +#define CIPRSCCTRL (*(volatile uint32_t *)0x4F00008C) /* Preview main-scaler control */ +#define CIPRTAREA (*(volatile uint32_t *)0x4F000090) /* Preview scaler target area */ +#define CIPRSTATUS (*(volatile uint32_t *)0x4F000098) /* Preview path status */ +#define CIIMGCPT (*(volatile uint32_t *)0x4F0000A0) /* Image capture enable command */ /* UART */ -#define ULCON0 (*(volatile unsigned long *)0x50000000) /* UART 0 line control */ -#define UCON0 (*(volatile unsigned long *)0x50000004) /* UART 0 control */ -#define UFCON0 (*(volatile unsigned long *)0x50000008) /* UART 0 FIFO control */ -#define UMCON0 (*(volatile unsigned long *)0x5000000C) /* UART 0 modem control */ -#define UTRSTAT0 (*(volatile unsigned long *)0x50000010) /* UART 0 Tx/Rx status */ -#define UERSTAT0 (*(volatile unsigned long *)0x50000014) /* UART 0 Rx error status */ -#define UFSTAT0 (*(volatile unsigned long *)0x50000018) /* UART 0 FIFO status */ -#define UMSTAT0 (*(volatile unsigned long *)0x5000001C) /* UART 0 modem status */ +#define ULCON0 (*(volatile uint32_t *)0x50000000) /* UART 0 line control */ +#define UCON0 (*(volatile uint32_t *)0x50000004) /* UART 0 control */ +#define UFCON0 (*(volatile uint32_t *)0x50000008) /* UART 0 FIFO control */ +#define UMCON0 (*(volatile uint32_t *)0x5000000C) /* UART 0 modem control */ +#define UTRSTAT0 (*(volatile uint32_t *)0x50000010) /* UART 0 Tx/Rx status */ +#define UERSTAT0 (*(volatile uint32_t *)0x50000014) /* UART 0 Rx error status */ +#define UFSTAT0 (*(volatile uint32_t *)0x50000018) /* UART 0 FIFO status */ +#define UMSTAT0 (*(volatile uint32_t *)0x5000001C) /* UART 0 modem status */ #define UTXH0 (*(volatile unsigned char *)0x50000020) /* UART 0 transmission hold */ #define URXH0 (*(volatile unsigned char *)0x50000024) /* UART 0 receive buffer */ -#define UBRDIV0 (*(volatile unsigned long *)0x50000028) /* UART 0 baud rate divisor */ -#define ULCON1 (*(volatile unsigned long *)0x50004000) /* UART 1 line control */ -#define UCON1 (*(volatile unsigned long *)0x50004004) /* UART 1 control */ -#define UFCON1 (*(volatile unsigned long *)0x50004008) /* UART 1 FIFO control */ -#define UMCON1 (*(volatile unsigned long *)0x5000400C) /* UART 1 modem control */ -#define UTRSTAT1 (*(volatile unsigned long *)0x50004010) /* UART 1 Tx/Rx status */ -#define UERSTAT1 (*(volatile unsigned long *)0x50004014) /* UART 1 Rx error status */ -#define UFSTAT1 (*(volatile unsigned long *)0x50004018) /* UART 1 FIFO status */ -#define UMSTAT1 (*(volatile unsigned long *)0x5000401C) /* UART 1 modem status */ +#define UBRDIV0 (*(volatile uint32_t *)0x50000028) /* UART 0 baud rate divisor */ +#define ULCON1 (*(volatile uint32_t *)0x50004000) /* UART 1 line control */ +#define UCON1 (*(volatile uint32_t *)0x50004004) /* UART 1 control */ +#define UFCON1 (*(volatile uint32_t *)0x50004008) /* UART 1 FIFO control */ +#define UMCON1 (*(volatile uint32_t *)0x5000400C) /* UART 1 modem control */ +#define UTRSTAT1 (*(volatile uint32_t *)0x50004010) /* UART 1 Tx/Rx status */ +#define UERSTAT1 (*(volatile uint32_t *)0x50004014) /* UART 1 Rx error status */ +#define UFSTAT1 (*(volatile uint32_t *)0x50004018) /* UART 1 FIFO status */ +#define UMSTAT1 (*(volatile uint32_t *)0x5000401C) /* UART 1 modem status */ #define UTXH1 (*(volatile unsigned char*)0x50004020) /* UART 1 transmission hold */ #define URXH1 (*(volatile unsigned char*)0x50004024) /* UART 1 receive buffer */ -#define UBRDIV1 (*(volatile unsigned long *)0x50004028) /* UART 1 baud rate divisor */ -#define ULCON2 (*(volatile unsigned long *)0x50008000) /* UART 2 line control */ -#define UCON2 (*(volatile unsigned long *)0x50008004) /* UART 2 control */ -#define UFCON2 (*(volatile unsigned long *)0x50008008) /* UART 2 FIFO control */ -#define UTRSTAT2 (*(volatile unsigned long *)0x50008010) /* UART 2 Tx/Rx status */ -#define UERSTAT2 (*(volatile unsigned long *)0x50008014) /* UART 2 Rx error status */ -#define UFSTAT2 (*(volatile unsigned long *)0x50008018) /* UART 2 FIFO status */ +#define UBRDIV1 (*(volatile uint32_t *)0x50004028) /* UART 1 baud rate divisor */ +#define ULCON2 (*(volatile uint32_t *)0x50008000) /* UART 2 line control */ +#define UCON2 (*(volatile uint32_t *)0x50008004) /* UART 2 control */ +#define UFCON2 (*(volatile uint32_t *)0x50008008) /* UART 2 FIFO control */ +#define UTRSTAT2 (*(volatile uint32_t *)0x50008010) /* UART 2 Tx/Rx status */ +#define UERSTAT2 (*(volatile uint32_t *)0x50008014) /* UART 2 Rx error status */ +#define UFSTAT2 (*(volatile uint32_t *)0x50008018) /* UART 2 FIFO status */ #define UTXH2 (*(volatile unsigned char*)0x50008020) /* UART 2 transmission hold */ #define URXH2 (*(volatile unsigned char*)0x50008024) /* UART 2 receive buffer */ -#define UBRDIV2 (*(volatile unsigned long *)0x50008028) /* UART 2 baud rate divisor */ +#define UBRDIV2 (*(volatile uint32_t *)0x50008028) /* UART 2 baud rate divisor */ /* PWM Timer */ -#define TCFG0 (*(volatile unsigned long *)0x51000000) /* Timer configuration */ -#define TCFG1 (*(volatile unsigned long *)0x51000004) /* Timer configuration */ -#define TCON (*(volatile unsigned long *)0x51000008) /* Timer control */ -#define TCNTB0 (*(volatile unsigned long *)0x5100000C) /* Timer count buffer 0 */ -#define TCMPB0 (*(volatile unsigned long *)0x51000010) /* Timer compare buffer 0 */ -#define TCNTO0 (*(volatile unsigned long *)0x51000014) /* Timer count observation 0 */ -#define TCNTB1 (*(volatile unsigned long *)0x51000018) /* Timer count buffer 1 */ -#define TCMPB1 (*(volatile unsigned long *)0x5100001C) /* Timer compare buffer 1 */ -#define TCNTO1 (*(volatile unsigned long *)0x51000020) /* Timer count observation 1 */ -#define TCNTB2 (*(volatile unsigned long *)0x51000024) /* Timer count buffer 2 */ -#define TCMPB2 (*(volatile unsigned long *)0x51000028) /* Timer compare buffer 2 */ -#define TCNTO2 (*(volatile unsigned long *)0x5100002C) /* Timer count observation 2 */ -#define TCNTB3 (*(volatile unsigned long *)0x51000030) /* Timer count buffer 3 */ -#define TCMPB3 (*(volatile unsigned long *)0x51000034) /* Timer compare buffer 3 */ -#define TCNTO3 (*(volatile unsigned long *)0x51000038) /* Timer count observation 3 */ -#define TCNTB4 (*(volatile unsigned long *)0x5100003C) /* Timer count buffer 4 */ -#define TCNTO4 (*(volatile unsigned long *)0x51000040) /* Timer count observation 4 */ +#define TCFG0 (*(volatile uint32_t *)0x51000000) /* Timer configuration */ +#define TCFG1 (*(volatile uint32_t *)0x51000004) /* Timer configuration */ +#define TCON (*(volatile uint32_t *)0x51000008) /* Timer control */ +#define TCNTB0 (*(volatile uint32_t *)0x5100000C) /* Timer count buffer 0 */ +#define TCMPB0 (*(volatile uint32_t *)0x51000010) /* Timer compare buffer 0 */ +#define TCNTO0 (*(volatile uint32_t *)0x51000014) /* Timer count observation 0 */ +#define TCNTB1 (*(volatile uint32_t *)0x51000018) /* Timer count buffer 1 */ +#define TCMPB1 (*(volatile uint32_t *)0x5100001C) /* Timer compare buffer 1 */ +#define TCNTO1 (*(volatile uint32_t *)0x51000020) /* Timer count observation 1 */ +#define TCNTB2 (*(volatile uint32_t *)0x51000024) /* Timer count buffer 2 */ +#define TCMPB2 (*(volatile uint32_t *)0x51000028) /* Timer compare buffer 2 */ +#define TCNTO2 (*(volatile uint32_t *)0x5100002C) /* Timer count observation 2 */ +#define TCNTB3 (*(volatile uint32_t *)0x51000030) /* Timer count buffer 3 */ +#define TCMPB3 (*(volatile uint32_t *)0x51000034) /* Timer compare buffer 3 */ +#define TCNTO3 (*(volatile uint32_t *)0x51000038) /* Timer count observation 3 */ +#define TCNTB4 (*(volatile uint32_t *)0x5100003C) /* Timer count buffer 4 */ +#define TCNTO4 (*(volatile uint32_t *)0x51000040) /* Timer count observation 4 */ /* USB Device */ @@ -447,24 +447,24 @@ /* Watchdog Timer */ -#define WTCON (*(volatile unsigned long *)0x53000000) /* Watchdog timer mode */ -#define WTDAT (*(volatile unsigned long *)0x53000004) /* Watchdog timer data */ -#define WTCNT (*(volatile unsigned long *)0x53000008) /* Watchdog timer count */ +#define WTCON (*(volatile uint32_t *)0x53000000) /* Watchdog timer mode */ +#define WTDAT (*(volatile uint32_t *)0x53000004) /* Watchdog timer data */ +#define WTCNT (*(volatile uint32_t *)0x53000008) /* Watchdog timer count */ /* IIC */ -#define IICCON (*(volatile unsigned long *)0x54000000) /* IIC control */ -#define IICSTAT (*(volatile unsigned long *)0x54000004) /* IIC status */ -#define IICADD (*(volatile unsigned long *)0x54000008) /* IIC address */ -#define IICDS (*(volatile unsigned long *)0x5400000C) /* IIC data shift */ -#define IICLC (*(volatile unsigned long *)0x54000010) /* IIC multi-master line control */ +#define IICCON (*(volatile uint32_t *)0x54000000) /* IIC control */ +#define IICSTAT (*(volatile uint32_t *)0x54000004) /* IIC status */ +#define IICADD (*(volatile uint32_t *)0x54000008) /* IIC address */ +#define IICDS (*(volatile uint32_t *)0x5400000C) /* IIC data shift */ +#define IICLC (*(volatile uint32_t *)0x54000010) /* IIC multi-master line control */ /* IIS */ -#define IISCON (*(volatile unsigned long *)0x55000000) /* IIS control */ -#define IISMOD (*(volatile unsigned long *)0x55000004) /* IIS mode */ -#define IISPSR (*(volatile unsigned long *)0x55000008) /* IIS prescaler */ -#define IISFCON (*(volatile unsigned long *)0x5500000C) /* IIS FIFO control */ +#define IISCON (*(volatile uint32_t *)0x55000000) /* IIS control */ +#define IISMOD (*(volatile uint32_t *)0x55000004) /* IIS mode */ +#define IISPSR (*(volatile uint32_t *)0x55000008) /* IIS prescaler */ +#define IISFCON (*(volatile uint32_t *)0x5500000C) /* IIS FIFO control */ #define IISFIFO (*(volatile unsigned short *)0x55000010) /* IIS FIFO entry */ #define IISCON_RIGHT_CHANNEL (1 << 8) @@ -502,49 +502,49 @@ /* I/O port */ -#define GPACON (*(volatile unsigned long *)0x56000000) /* Port A control */ -#define GPADAT (*(volatile unsigned long *)0x56000004) /* Port A data */ -#define GPBCON (*(volatile unsigned long *)0x56000010) /* Port B control */ -#define GPBDAT (*(volatile unsigned long *)0x56000014) /* Port B data */ -#define GPBUP (*(volatile unsigned long *)0x56000018) /* Pull-up control B */ -#define GPCCON (*(volatile unsigned long *)0x56000020) /* Port C control */ -#define GPCDAT (*(volatile unsigned long *)0x56000024) /* Port C data */ -#define GPCUP (*(volatile unsigned long *)0x56000028) /* Pull-up control C */ -#define GPDCON (*(volatile unsigned long *)0x56000030) /* Port D control */ -#define GPDDAT (*(volatile unsigned long *)0x56000034) /* Port D data */ -#define GPDUP (*(volatile unsigned long *)0x56000038) /* Pull-up control D */ -#define GPECON (*(volatile unsigned long *)0x56000040) /* Port E control */ -#define GPEDAT (*(volatile unsigned long *)0x56000044) /* Port E data */ -#define GPEUP (*(volatile unsigned long *)0x56000048) /* Pull-up control E */ -#define GPFCON (*(volatile unsigned long *)0x56000050) /* Port F control */ -#define GPFDAT (*(volatile unsigned long *)0x56000054) /* Port F data */ -#define GPFUP (*(volatile unsigned long *)0x56000058) /* Pull-up control F */ -#define GPGCON (*(volatile unsigned long *)0x56000060) /* Port G control */ -#define GPGDAT (*(volatile unsigned long *)0x56000064) /* Port G data */ -#define GPGUP (*(volatile unsigned long *)0x56000068) /* Pull-up control G */ -#define GPHCON (*(volatile unsigned long *)0x56000070) /* Port H control */ -#define GPHDAT (*(volatile unsigned long *)0x56000074) /* Port H data */ -#define GPHUP (*(volatile unsigned long *)0x56000078) /* Pull-up control H */ -#define MISCCR (*(volatile unsigned long *)0x56000080) /* Miscellaneous control */ -#define DCLKCON (*(volatile unsigned long *)0x56000084) /* DCLK0/1 control */ -#define EXTINT0 (*(volatile unsigned long *)0x56000088) /* External interrupt control register 0 */ -#define EXTINT1 (*(volatile unsigned long *)0x5600008C) /* External interrupt control register 1 */ -#define EXTINT2 (*(volatile unsigned long *)0x56000090) /* External interrupt control register 2 */ -#define EINTFLT0 (*(volatile unsigned long *)0x56000094) /* Reserved */ -#define EINTFLT1 (*(volatile unsigned long *)0x56000098) /* Reserved */ -#define EINTFLT2 (*(volatile unsigned long *)0x5600009C) /* External interrupt filter control register 2 */ -#define EINTFLT3 (*(volatile unsigned long *)0x560000A0) /* External interrupt filter control register 3 */ -#define EINTMASK (*(volatile unsigned long *)0x560000A4) /* External interrupt mask */ -#define EINTPEND (*(volatile unsigned long *)0x560000A8) /* External interrupt pending */ -#define GSTATUS0 (*(volatile unsigned long *)0x560000AC) /* External pin status */ -#define GSTATUS1 (*(volatile unsigned long *)0x560000B0) /* Chip ID */ -#define GSTATUS2 (*(volatile unsigned long *)0x560000B4) /* Reset status */ -#define GSTATUS3 (*(volatile unsigned long *)0x560000B8) /* Inform register */ -#define GSTATUS4 (*(volatile unsigned long *)0x560000BC) /* Inform register */ -#define MSLCON (*(volatile unsigned long *)0x560000CC) /* Memory sleep control register */ -#define GPJCON (*(volatile unsigned long *)0x560000D0) /* Port J control */ -#define GPJDAT (*(volatile unsigned long *)0x560000D4) /* Port J data */ -#define GPJUP (*(volatile unsigned long *)0x560000D8) /* Pull-up control J */ +#define GPACON (*(volatile uint32_t *)0x56000000) /* Port A control */ +#define GPADAT (*(volatile uint32_t *)0x56000004) /* Port A data */ +#define GPBCON (*(volatile uint32_t *)0x56000010) /* Port B control */ +#define GPBDAT (*(volatile uint32_t *)0x56000014) /* Port B data */ +#define GPBUP (*(volatile uint32_t *)0x56000018) /* Pull-up control B */ +#define GPCCON (*(volatile uint32_t *)0x56000020) /* Port C control */ +#define GPCDAT (*(volatile uint32_t *)0x56000024) /* Port C data */ +#define GPCUP (*(volatile uint32_t *)0x56000028) /* Pull-up control C */ +#define GPDCON (*(volatile uint32_t *)0x56000030) /* Port D control */ +#define GPDDAT (*(volatile uint32_t *)0x56000034) /* Port D data */ +#define GPDUP (*(volatile uint32_t *)0x56000038) /* Pull-up control D */ +#define GPECON (*(volatile uint32_t *)0x56000040) /* Port E control */ +#define GPEDAT (*(volatile uint32_t *)0x56000044) /* Port E data */ +#define GPEUP (*(volatile uint32_t *)0x56000048) /* Pull-up control E */ +#define GPFCON (*(volatile uint32_t *)0x56000050) /* Port F control */ +#define GPFDAT (*(volatile uint32_t *)0x56000054) /* Port F data */ +#define GPFUP (*(volatile uint32_t *)0x56000058) /* Pull-up control F */ +#define GPGCON (*(volatile uint32_t *)0x56000060) /* Port G control */ +#define GPGDAT (*(volatile uint32_t *)0x56000064) /* Port G data */ +#define GPGUP (*(volatile uint32_t *)0x56000068) /* Pull-up control G */ +#define GPHCON (*(volatile uint32_t *)0x56000070) /* Port H control */ +#define GPHDAT (*(volatile uint32_t *)0x56000074) /* Port H data */ +#define GPHUP (*(volatile uint32_t *)0x56000078) /* Pull-up control H */ +#define MISCCR (*(volatile uint32_t *)0x56000080) /* Miscellaneous control */ +#define DCLKCON (*(volatile uint32_t *)0x56000084) /* DCLK0/1 control */ +#define EXTINT0 (*(volatile uint32_t *)0x56000088) /* External interrupt control register 0 */ +#define EXTINT1 (*(volatile uint32_t *)0x5600008C) /* External interrupt control register 1 */ +#define EXTINT2 (*(volatile uint32_t *)0x56000090) /* External interrupt control register 2 */ +#define EINTFLT0 (*(volatile uint32_t *)0x56000094) /* Reserved */ +#define EINTFLT1 (*(volatile uint32_t *)0x56000098) /* Reserved */ +#define EINTFLT2 (*(volatile uint32_t *)0x5600009C) /* External interrupt filter control register 2 */ +#define EINTFLT3 (*(volatile uint32_t *)0x560000A0) /* External interrupt filter control register 3 */ +#define EINTMASK (*(volatile uint32_t *)0x560000A4) /* External interrupt mask */ +#define EINTPEND (*(volatile uint32_t *)0x560000A8) /* External interrupt pending */ +#define GSTATUS0 (*(volatile uint32_t *)0x560000AC) /* External pin status */ +#define GSTATUS1 (*(volatile uint32_t *)0x560000B0) /* Chip ID */ +#define GSTATUS2 (*(volatile uint32_t *)0x560000B4) /* Reset status */ +#define GSTATUS3 (*(volatile uint32_t *)0x560000B8) /* Inform register */ +#define GSTATUS4 (*(volatile uint32_t *)0x560000BC) /* Inform register */ +#define MSLCON (*(volatile uint32_t *)0x560000CC) /* Memory sleep control register */ +#define GPJCON (*(volatile uint32_t *)0x560000D0) /* Port J control */ +#define GPJDAT (*(volatile uint32_t *)0x560000D4) /* Port J data */ +#define GPJUP (*(volatile uint32_t *)0x560000D8) /* Pull-up control J */ /* RTC */ @@ -567,52 +567,52 @@ /* A/D Converter */ -#define ADCCON (*(volatile unsigned long *)0x58000000) /* ADC control */ -#define ADCTSC (*(volatile unsigned long *)0x58000004) /* ADC touch screen control */ -#define ADCDLY (*(volatile unsigned long *)0x58000008) /* ADC start or interval delay */ -#define ADCDAT0 (*(volatile unsigned long *)0x5800000C) /* ADC conversion data */ -#define ADCDAT1 (*(volatile unsigned long *)0x58000010) /* ADC conversion data */ -#define ADCUPDN (*(volatile unsigned long *)0x58000014) /* Stylus up or down interrupt status */ +#define ADCCON (*(volatile uint32_t *)0x58000000) /* ADC control */ +#define ADCTSC (*(volatile uint32_t *)0x58000004) /* ADC touch screen control */ +#define ADCDLY (*(volatile uint32_t *)0x58000008) /* ADC start or interval delay */ +#define ADCDAT0 (*(volatile uint32_t *)0x5800000C) /* ADC conversion data */ +#define ADCDAT1 (*(volatile uint32_t *)0x58000010) /* ADC conversion data */ +#define ADCUPDN (*(volatile uint32_t *)0x58000014) /* Stylus up or down interrupt status */ /* SPI */ -#define SPCON0 (*(volatile unsigned long *)0x59000000) /* SPI control */ -#define SPSTA0 (*(volatile unsigned long *)0x59000004) /* SPI status */ -#define SPPIN0 (*(volatile unsigned long *)0x59000008) /* SPI pin control */ -#define SPPRE0 (*(volatile unsigned long *)0x5900000C) /* SPI baud rate prescaler */ -#define SPTDAT0 (*(volatile unsigned long *)0x59000010) /* SPI Tx data */ -#define SPRDAT0 (*(volatile unsigned long *)0x59000014) /* SPI Rx data */ -#define SPCON1 (*(volatile unsigned long *)0x59000020) /* SPI control */ -#define SPSTA1 (*(volatile unsigned long *)0x59000024) /* SPI status */ -#define SPPIN1 (*(volatile unsigned long *)0x59000028) /* SPI pin control */ -#define SPPRE1 (*(volatile unsigned long *)0x5900002C) /* SPI baud rate prescaler */ -#define SPTDAT1 (*(volatile unsigned long *)0x59000030) /* SPI Tx data */ -#define SPRDAT1 (*(volatile unsigned long *)0x59000034) /* SPI Rx data */ +#define SPCON0 (*(volatile uint32_t *)0x59000000) /* SPI control */ +#define SPSTA0 (*(volatile uint32_t *)0x59000004) /* SPI status */ +#define SPPIN0 (*(volatile uint32_t *)0x59000008) /* SPI pin control */ +#define SPPRE0 (*(volatile uint32_t *)0x5900000C) /* SPI baud rate prescaler */ +#define SPTDAT0 (*(volatile uint32_t *)0x59000010) /* SPI Tx data */ +#define SPRDAT0 (*(volatile uint32_t *)0x59000014) /* SPI Rx data */ +#define SPCON1 (*(volatile uint32_t *)0x59000020) /* SPI control */ +#define SPSTA1 (*(volatile uint32_t *)0x59000024) /* SPI status */ +#define SPPIN1 (*(volatile uint32_t *)0x59000028) /* SPI pin control */ +#define SPPRE1 (*(volatile uint32_t *)0x5900002C) /* SPI baud rate prescaler */ +#define SPTDAT1 (*(volatile uint32_t *)0x59000030) /* SPI Tx data */ +#define SPRDAT1 (*(volatile uint32_t *)0x59000034) /* SPI Rx data */ /* SD Interface */ -#define SDICON (*(volatile unsigned long *)0x5A000000) /* SDI control */ -#define SDIPRE (*(volatile unsigned long *)0x5A000004) /* SDI baud rate prescaler */ -#define SDICARG (*(volatile unsigned long *)0x5A000008) /* SDI command argument */ -#define SDICCON (*(volatile unsigned long *)0x5A00000C) /* SDI command control */ -#define SDICSTA (*(volatile unsigned long *)0x5A000010) /* SDI command status */ -#define SDIRSP0 (*(volatile unsigned long *)0x5A000014) /* SDI response */ -#define SDIRSP1 (*(volatile unsigned long *)0x5A000018) /* SDI response */ -#define SDIRSP2 (*(volatile unsigned long *)0x5A00001C) /* SDI response */ -#define SDIRSP3 (*(volatile unsigned long *)0x5A000020) /* SDI response */ -#define SDIDTIMER (*(volatile unsigned long *)0x5A000024) /* SDI data / busy timer */ -#define SDIBSIZE (*(volatile unsigned long *)0x5A000028) /* SDI block size */ -#define SDIDCON (*(volatile unsigned long *)0x5A00002C) /* SDI data control */ -#define SDIDCNT (*(volatile unsigned long *)0x5A000030) /* SDI data remain counter */ -#define SDIDSTA (*(volatile unsigned long *)0x5A000034) /* SDI data status */ -#define SDIFSTA (*(volatile unsigned long *)0x5A000038) /* SDI FIFO status */ -#define SDIIMSK (*(volatile unsigned long *)0x5A00003C) /* SDI interrupt mask */ +#define SDICON (*(volatile uint32_t *)0x5A000000) /* SDI control */ +#define SDIPRE (*(volatile uint32_t *)0x5A000004) /* SDI baud rate prescaler */ +#define SDICARG (*(volatile uint32_t *)0x5A000008) /* SDI command argument */ +#define SDICCON (*(volatile uint32_t *)0x5A00000C) /* SDI command control */ +#define SDICSTA (*(volatile uint32_t *)0x5A000010) /* SDI command status */ +#define SDIRSP0 (*(volatile uint32_t *)0x5A000014) /* SDI response */ +#define SDIRSP1 (*(volatile uint32_t *)0x5A000018) /* SDI response */ +#define SDIRSP2 (*(volatile uint32_t *)0x5A00001C) /* SDI response */ +#define SDIRSP3 (*(volatile uint32_t *)0x5A000020) /* SDI response */ +#define SDIDTIMER (*(volatile uint32_t *)0x5A000024) /* SDI data / busy timer */ +#define SDIBSIZE (*(volatile uint32_t *)0x5A000028) /* SDI block size */ +#define SDIDCON (*(volatile uint32_t *)0x5A00002C) /* SDI data control */ +#define SDIDCNT (*(volatile uint32_t *)0x5A000030) /* SDI data remain counter */ +#define SDIDSTA (*(volatile uint32_t *)0x5A000034) /* SDI data status */ +#define SDIFSTA (*(volatile uint32_t *)0x5A000038) /* SDI FIFO status */ +#define SDIIMSK (*(volatile uint32_t *)0x5A00003C) /* SDI interrupt mask */ /* SDI data - LE = Little Endian, BE = Big Endian */ -#define SDIDAT_LLE (*(volatile unsigned long *)0x5A000040) /* 32 bit */ +#define SDIDAT_LLE (*(volatile uint32_t *)0x5A000040) /* 32 bit */ #define SDIDAT_HLE (*(volatile unsigned short *)0x5A000044) /* 16 */ #define SDIDAT_BLE (*(volatile unsigned char *)0x5A000048) /* 8 */ -#define SDIDAT_LBE (*(volatile unsigned long *)0x5A00004C) /* 32 */ +#define SDIDAT_LBE (*(volatile uint32_t *)0x5A00004C) /* 32 */ #define SDIDAT_HBE (*(volatile unsigned short *)0x5A000041) /* 16 */ #define SDIDAT_BBE (*(volatile unsigned char *)0x5A000043) /* 8 */ @@ -714,14 +714,14 @@ /* AC97 Audio-CODEC Interface */ -#define AC_GLBCTRL (*(volatile unsigned long *)0x5B000000) /* AC97 global control register */ -#define AC_GLBSTAT (*(volatile unsigned long *)0x5B000004) /* AC97 global status register */ -#define AC_CODEC_CMD (*(volatile unsigned long *)0x5B000008) /* AC97 codec command register */ -#define AC_CODEC_STAT (*(volatile unsigned long *)0x5B00000C) /* AC97 codec status register */ -#define AC_PCMADDR (*(volatile unsigned long *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */ -#define AC_MICADDR (*(volatile unsigned long *)0x5B000014) /* AC97 mic in channel FIFO address register */ -#define AC_PCMDATA (*(volatile unsigned long *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */ -#define AC_MICDATA (*(volatile unsigned long *)0x5B00001C) /* AC97 MIC in channel FIFO data register */ +#define AC_GLBCTRL (*(volatile uint32_t *)0x5B000000) /* AC97 global control register */ +#define AC_GLBSTAT (*(volatile uint32_t *)0x5B000004) /* AC97 global status register */ +#define AC_CODEC_CMD (*(volatile uint32_t *)0x5B000008) /* AC97 codec command register */ +#define AC_CODEC_STAT (*(volatile uint32_t *)0x5B00000C) /* AC97 codec status register */ +#define AC_PCMADDR (*(volatile uint32_t *)0x5B000010) /* AC97 PCM out/in channel FIFO address register */ +#define AC_MICADDR (*(volatile uint32_t *)0x5B000014) /* AC97 mic in channel FIFO address register */ +#define AC_PCMDATA (*(volatile uint32_t *)0x5B000018) /* AC97 PCM out/in channel FIFO data register */ +#define AC_MICDATA (*(volatile uint32_t *)0x5B00001C) /* AC97 MIC in channel FIFO data register */ /* Memory banks */ diff --git a/firmware/target/arm/as3525/app.lds b/firmware/target/arm/as3525/app.lds index 4807855198..a4f9c06d49 100644 --- a/firmware/target/arm/as3525/app.lds +++ b/firmware/target/arm/as3525/app.lds @@ -1,3 +1,4 @@ +#define __ASSEMBLER__ #include "config.h" #include "cpu.h" diff --git a/firmware/target/arm/as3525/ascodec-as3525.c b/firmware/target/arm/as3525/ascodec-as3525.c index 6076505acb..1cc584fa72 100644 --- a/firmware/target/arm/as3525/ascodec-as3525.c +++ b/firmware/target/arm/as3525/ascodec-as3525.c @@ -127,7 +127,7 @@ static void ascodec_int_audio_cb(struct ascodec_request *req); void INT_I2C_AUDIO(void); static struct ascodec_request as_audio_req; static struct semaphore adc_done_sem; -static unsigned long ascodec_enrd0_shadow = 0; +static uint32_t ascodec_enrd0_shadow = 0; static void ascodec_wait_cb(struct ascodec_request *req); diff --git a/firmware/target/arm/as3525/boot.lds b/firmware/target/arm/as3525/boot.lds index 9861ef2125..41737f5112 100644 --- a/firmware/target/arm/as3525/boot.lds +++ b/firmware/target/arm/as3525/boot.lds @@ -1,3 +1,4 @@ +#define __ASSEMBLER__ #include "config.h" #include "cpu.h" diff --git a/firmware/target/arm/imx233/sdmmc-imx233.c b/firmware/target/arm/imx233/sdmmc-imx233.c index 02f59a50f4..d5d5a57a10 100644 --- a/firmware/target/arm/imx233/sdmmc-imx233.c +++ b/firmware/target/arm/imx233/sdmmc-imx233.c @@ -356,7 +356,7 @@ static bool send_cmd(int drive, uint8_t cmd, uint32_t arg, uint32_t flags, uint3 static int wait_for_state(int drive, unsigned state) { - unsigned long response; + uint32_t response; unsigned int timeout = current_tick + 5*HZ; int cmd_retry = 10; int next_yield = current_tick + MIN_YIELD_PERIOD; @@ -424,21 +424,21 @@ static int init_sd_card(int drive) /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */ if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)), - MCI_ACMD|MCI_NOCRC|MCI_RESP, &SDMMC_INFO(drive).ocr)) + MCI_ACMD|MCI_NOCRC|MCI_RESP, (uint32_t*)&SDMMC_INFO(drive).ocr)) return -100; } while(!(SDMMC_INFO(drive).ocr & (1<<31))); /* CMD2 send CID */ - if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, SDMMC_INFO(drive).cid)) + if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, (uint32_t*)SDMMC_INFO(drive).cid)) return -3; /* CMD3 send RCA */ - if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &SDMMC_INFO(drive).rca)) + if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, (uint32_t*)&SDMMC_INFO(drive).rca)) return -4; /* CMD9 send CSD */ if(!send_cmd(drive, SD_SEND_CSD, SDMMC_RCA(drive), MCI_RESP|MCI_LONG_RESP, - SDMMC_INFO(drive).csd)) + (uint32_t*)SDMMC_INFO(drive).csd)) return -9; sd_parse_csd(&SDMMC_INFO(drive)); diff --git a/firmware/target/arm/imx31/ccm-imx31.c b/firmware/target/arm/imx31/ccm-imx31.c index 00a7d859b1..31748de4e7 100644 --- a/firmware/target/arm/imx31/ccm-imx31.c +++ b/firmware/target/arm/imx31/ccm-imx31.c @@ -32,7 +32,7 @@ enum IMX31_PLLS ccm_get_src_pll(void) void ccm_module_clock_gating(enum IMX31_CG_LIST cg, enum IMX31_CG_MODES mode) { - volatile unsigned long *reg; + volatile uint32_t *reg; unsigned long mask; int shift; @@ -112,7 +112,7 @@ unsigned int ccm_get_ata_clk(void) void ccm_set_mcupll_and_pdr(unsigned long pllctl, unsigned long pdr) { unsigned int pll = ccm_get_src_pll(); - volatile unsigned long *pllreg = &(&CCM_MPCTL)[pll]; + volatile uint32_t *pllreg = &(&CCM_MPCTL)[pll]; unsigned long fref = ccm_get_pll_ref_clk_rate(); unsigned long curfreq = ccm_calc_pll_rate(fref, *pllreg); unsigned long newfreq = ccm_calc_pll_rate(fref, pllctl); diff --git a/firmware/target/arm/imx31/dvfs_dptc-imx31.c b/firmware/target/arm/imx31/dvfs_dptc-imx31.c index 3f9e9a3dd8..5a703b65db 100644 --- a/firmware/target/arm/imx31/dvfs_dptc-imx31.c +++ b/firmware/target/arm/imx31/dvfs_dptc-imx31.c @@ -620,7 +620,7 @@ void dvfs_int_mask(bool mask) /* Set a signal load tracking weight */ void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value) { - volatile unsigned long *reg_p = &CCM_LTR2; + volatile uint32_t *reg_p = &CCM_LTR2; unsigned int shift = 3 * index; if (index < 9) @@ -639,7 +639,7 @@ void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value) /* Return a signal load tracking weight */ unsigned long dvfs_get_lt_weight(enum DVFS_LT_SIGS index) { - volatile unsigned long *reg_p = &CCM_LTR2; + volatile uint32_t *reg_p = &CCM_LTR2; unsigned int shift = 3 * index; if (index < 9) diff --git a/firmware/target/arm/imx31/gigabeat-s/button-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/button-gigabeat-s.c index cdd6da041b..0caf840330 100644 --- a/firmware/target/arm/imx31/gigabeat-s/button-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/button-gigabeat-s.c @@ -35,7 +35,7 @@ static bool initialized = false; #endif -static unsigned long ext_btn = BUTTON_NONE; /* Buttons not on KPP */ +static uint32_t ext_btn = BUTTON_NONE; /* Buttons not on KPP */ static bool hold_button = false; #ifndef BOOTLOADER static bool hold_button_old = false; diff --git a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c index 81f150acd7..79e16a5239 100644 --- a/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c +++ b/firmware/target/arm/imx31/gigabeat-s/power-gigabeat-s.c @@ -33,7 +33,7 @@ #include "fmradio_i2c.h" #endif -static unsigned long power_status = POWER_INPUT_NONE; +static uint32_t power_status = POWER_INPUT_NONE; /* Detect which power sources are present. */ unsigned int power_input_status(void) diff --git a/firmware/target/arm/imx31/gpio-imx31.c b/firmware/target/arm/imx31/gpio-imx31.c index 7a7363be88..9e1992beab 100644 --- a/firmware/target/arm/imx31/gpio-imx31.c +++ b/firmware/target/arm/imx31/gpio-imx31.c @@ -44,7 +44,7 @@ static __attribute__((interrupt("IRQ"))) void GPIO3_HANDLER(void); static struct gpio_module_desc { - volatile unsigned long * const base; /* Module base address */ + volatile uint32_t * const base; /* Module base address */ void (* const handler)(void); /* Interrupt function */ const struct gpio_event *events; /* Event handler list */ unsigned long enabled; /* Enabled event mask */ @@ -55,7 +55,7 @@ static struct gpio_module_desc { #if (GPIO_EVENT_MASK & USE_GPIO1_EVENTS) [GPIO1_NUM] = &(struct gpio_module_desc) { - .base = (unsigned long *)GPIO1_BASE_ADDR, + .base = (uint32_t *)GPIO1_BASE_ADDR, .ints = INT_GPIO1, .handler = GPIO1_HANDLER, .int_priority = GPIO1_INT_PRIO @@ -63,7 +63,7 @@ static struct gpio_module_desc #endif #if (GPIO_EVENT_MASK & USE_GPIO2_EVENTS) [GPIO2_NUM] = &(struct gpio_module_desc) { - .base = (unsigned long *)GPIO2_BASE_ADDR, + .base = (uint32_t *)GPIO2_BASE_ADDR, .ints = INT_GPIO2, .handler = GPIO2_HANDLER, .int_priority = GPIO2_INT_PRIO @@ -71,7 +71,7 @@ static struct gpio_module_desc #endif #if (GPIO_EVENT_MASK & USE_GPIO3_EVENTS) [GPIO3_NUM] = &(struct gpio_module_desc) { - .base = (unsigned long *)GPIO3_BASE_ADDR, + .base = (uint32_t *)GPIO3_BASE_ADDR, .ints = INT_GPIO3, .handler = GPIO3_HANDLER, .int_priority = GPIO3_INT_PRIO, @@ -97,7 +97,7 @@ static const struct gpio_event * event_from_id( static void gpio_call_events(enum gpio_module_number gpio) { const struct gpio_module_desc * const desc = gpio_descs[gpio]; - volatile unsigned long * const base = desc->base; + volatile uint32_t * const base = desc->base; /* Send only events that are not masked */ unsigned long pnd = base[GPIO_ISR] & base[GPIO_IMR]; @@ -180,7 +180,7 @@ bool gpio_enable_event(enum gpio_id id, bool enable) if (!event) return false; - volatile unsigned long * const base = desc->base; + volatile uint32_t * const base = desc->base; unsigned long num = id % 32; unsigned long mask = 1ul << num; @@ -205,7 +205,7 @@ bool gpio_enable_event(enum gpio_id id, bool enable) } else { - volatile unsigned long *icrp = &base[GPIO_ICR + num / 16]; + volatile uint32_t *icrp = &base[GPIO_ICR + num / 16]; unsigned int shift = 2*(num % 16); bitmod32(icrp, event->sense << shift, 0x3 << shift); base[GPIO_EDGE_SEL] &= ~mask; diff --git a/firmware/target/arm/imx31/gpio-imx31.h b/firmware/target/arm/imx31/gpio-imx31.h index e02896f4c3..bd0b324caa 100644 --- a/firmware/target/arm/imx31/gpio-imx31.h +++ b/firmware/target/arm/imx31/gpio-imx31.h @@ -191,10 +191,10 @@ struct gpio_event #endif /* DEFINE_GPIO_VECTOR_TABLE */ #define GPIO_BASE_ADDR \ - (volatile unsigned long * const [GPIO_NUM_GPIO]) { \ - (volatile unsigned long *)GPIO1_BASE_ADDR, \ - (volatile unsigned long *)GPIO2_BASE_ADDR, \ - (volatile unsigned long *)GPIO3_BASE_ADDR } + (volatile uint32_t * const [GPIO_NUM_GPIO]) { \ + (volatile uint32_t *)GPIO1_BASE_ADDR, \ + (volatile uint32_t *)GPIO2_BASE_ADDR, \ + (volatile uint32_t *)GPIO3_BASE_ADDR } #define GPIO_DR (0x00 / sizeof (unsigned long)) /* 00h */ #define GPIO_GDIR (0x04 / sizeof (unsigned long)) /* 04h */ diff --git a/firmware/target/arm/imx31/iomuxc-imx31.c b/firmware/target/arm/imx31/iomuxc-imx31.c index 412693e221..eb1066e004 100644 --- a/firmware/target/arm/imx31/iomuxc-imx31.c +++ b/firmware/target/arm/imx31/iomuxc-imx31.c @@ -32,7 +32,7 @@ void iomuxc_set_pin_mux(enum IMX31_IOMUXC_PINS pin, unsigned long index = pin / 4; unsigned int shift = 8*(pin % 4); - bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0xc) + index, + bitmod32((uint32_t *)(IOMUXC_BASE_ADDR + 0xc) + index, mux << shift, IOMUXC_MUX_MASK << shift); } @@ -45,6 +45,6 @@ void iomuxc_set_pad_config(enum IMX31_IOMUXC_PINS pin, unsigned long index = padoffs / 3; unsigned int shift = 10*(padoffs % 3); - bitmod32((unsigned long *)(IOMUXC_BASE_ADDR + 0x154) + index, + bitmod32((uint32_t *)(IOMUXC_BASE_ADDR + 0x154) + index, config << shift, IOMUXC_PAD_MASK << shift); } diff --git a/firmware/target/arm/imx31/sdma-imx31.c b/firmware/target/arm/imx31/sdma-imx31.c index d3e6233a4b..ffe75ee55c 100644 --- a/firmware/target/arm/imx31/sdma-imx31.c +++ b/firmware/target/arm/imx31/sdma-imx31.c @@ -36,7 +36,7 @@ /* Cut down to bare bones essentials */ /* Mask of channels with callback enabled */ -static unsigned long sdma_enabled_ints = 0; +static uint32_t sdma_enabled_ints = 0; /* One channel control block per channel in physically mapped device RAM */ static struct channel_control_block ccb_array[CH_NUM] NOCACHEBSS_ATTR; /* Channel 0 (command channel) data */ -- rockbox-cvs mailing list [email protected] https://lists.haxx.se/mailman/listinfo/rockbox-cvs