stm32h7: sdmmc: handle CMD12 before second cache discard
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commit 11817f99f80492ae9990e625828d7a161aea9928 Author: Aidan MacDonald <[email protected]> Date: Fri Aug 14 20:30:05 2026 +0100 stm32h7: sdmmc: handle CMD12 before second cache discard Because DMA is still running until CMD12 is issued the second cache discard must occur after CMD12, otherwise the cache may contain a stale copy of data. While the buffer is garbage at this point it's probably not a good idea to leave the buffer in a weird state where the cache doesn't match what's in RAM. Change-Id: I7caf91d17631c92686ef0ad6f148e6c1d1bcbfa0 diff --git a/firmware/target/arm/stm32/sdmmc-stm32h7.c b/firmware/target/arm/stm32/sdmmc-stm32h7.c index 13fd606eb4..ed93f229df 100644 --- a/firmware/target/arm/stm32/sdmmc-stm32h7.c +++ b/firmware/target/arm/stm32/sdmmc-stm32h7.c @@ -378,16 +378,8 @@ int stm32h7_sdmmc_submit_command(void *controller, /* Wait for command completion */ semaphore_wait(&ctl->sem, TIMEOUT_BLOCK); - /* - * Discard data from speculative reads that may have - * accessed the buffer during the DMA transfer. - */ + /* Save original command status code */ int cmd_error = ctl->cmd_error; - if (cmd_error == SDMMC_STATUS_OK) - { - if (SDMMC_DATA_DIR(cmd->flags) == SDMMC_DATA_READ) - discard_dcache_range(buff_addr, buff_size); - } /* * If a data transfer command fails we need to issue CMD12 @@ -409,6 +401,15 @@ int stm32h7_sdmmc_submit_command(void *controller, stm32h7_sdmmc_submit_command(ctl, &cmd12, NULL); } + /* + * Discard data from speculative reads that may have + * accessed the buffer during the DMA transfer. Must + * be done after the CMD12 above otherwise the cache + * may end up out of sync with main memory. + */ + if (SDMMC_DATA_DIR(cmd->flags) == SDMMC_DATA_READ) + discard_dcache_range(buff_addr, buff_size); + /* Return error from original command */ return cmd_error; } -- rockbox-cvs mailing list [email protected] https://lists.haxx.se/mailman/listinfo/rockbox-cvs