Re: [PATCH] Add riscv-sim.exp

We are happy (in principle) to add this support to DejaGNU, however the 
FSF does not currently have a copyright assignment for changes to 
DejaGNU from SiFive or from you.  I note that riscv-sim.exp has an FSF 
copyright notice, but we do not have the papers to substantiate that 
notice for contributions to DejaGNU, which is considered to be distinct 
from the other toolchain packages.  (I presume the SiFive had a 
significant role in adding RISC-V support to the toolchain, and so has 
assigned their changes there, but DejaGNU fell through the proverbial 
cracks.)  We will need the legal papers completed before we can accept 
your contribution.

While waiting for the legal papers to be completed, I do have some 
technical questions:
    Do I correctly infer that this patch works with the sim tool shipped 
with GDB?
    Is similar support planned for QEMU and/or Spike?
    There is some generic QEMU support in Git master in the file 
baseboards/qemu.exp, but its RISC-V section is in a list of other 
platforms QEMU supports where we are currently unsure of the correct 
target patterns.  Could you take a look at those and align them with the 
RISC-V toolchain?


-- Jacob