Re: Help needed for porting opcodes for CISC architecture

Usha Gupta <[email protected]> writes:

> [...]
> (default-insn-bitsize 8)
> (base-insn-bitsize 16)
> (default-insn-word-bitsize 16 )
> (word-bitsize 16 )

OK (though you might need to raise base-insn-bitsize).

> [...]
> Here are some of the instruction formats :
>
> 1-byte instruction:
> 1)      IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of
> the operand is fixed register, implied from the opcode)
> 2)      IIIddddd - 3 bits opcode, 5 bit displacement
>
> 2-byte instruction:
> 1)      IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register  operand
> (source), 5-bit opcode, 3-bit register operand (destination)
>
> How do I define  instructions of varying length?

Presumably those IIIII's don't overlap - i.e., the hardware can tell
from the first byte that it's a 2-byte instruction (and more opcode
bits need to be fetched).  In cgen, instruction opcodes need not be
single fields nor contiguous; just specify one ifield per unique
opcode piece.

- FChE