Macro with same operands is misbehaving

Hi,

Before going ahead and start modifying CGEN I wanted to confirm if one
can implement something like this with the current CGEN.

Take a floating point instruction like the RISC-V `fsgnj.s f0, f1, 2`.
`fmv.s` is a floating point move instruction that can be defined in
terms of `fsgnj.s` as:
`fmv.s f0, f1` == `fsgnj.s f0, f1, f1`.

If I define the instruction fsgnj.s and followed by fmv.s macro, during
disassembly `fsgnj.s` is always chosen, although assembly works fine.
If on the other hand I define `fmv.s` macro followed by the instruction,
assembly works fine again but all disassembly is broken because the
instruction `fsgnj.s ft0, ft1, ft2` will be disassembled as `fmv.s ft0,
ft1` - i.e. ft2 is ignored.

I can't find a way to say: `fmv.s` matches for disassembly but only if
`f1` == `f2` in `fsgnj.s f0, f1, f2`.

I tried to actually define `fmv.s` as a new instruction instead of a
macro but it doesn't work. Actually the same problem occurs because
bitwise `fmv.s` is going to be the same as a `fsgnj.s` with two
registers being the same.

How can I tell the disassembler in CGEN about this `fmv.s` constraint?

-- 
Paulo Matos