Re: BUG: non-fixed-length ISAs are unsupported for now
Sergey Belyashov via Cgen <[email protected]> Mon, 27 Apr 2020 20:52:11 +0300
| Newsgroups | gmane.comp.tools.cgen.devel |
|---|---|
| Message-ID | <CAOe0RDxY-ZOavy6xJo+3nGOeCXc3_tiPAQrZbzBfzHc3wARcNQ@mail.gmail.com> |
I have tried to increase base-insn-bitsize to 32, but nothing is changed. z80_cgen_insn_opcode_table in z80-opc.c contains sum of instruction bytes: 0xED 0x45 -> 0x132 Best regards, Sergey Belyashov пн, 27 апр. 2020 г. в 20:00, Sergey Belyashov <[email protected]>: > Hi, > Z80 has istructions from 1 byte (nop for example) up to 4 bytes long (eZ80 > up to 6 bytes) including operands 0..2 bytes (eZ80 0..3 bytes). So > base-insn-bitsize is set to 8. And it is not enought for 1-3 bytes (eZ80 > 1-4) insn code size (w/o immediate operands). > > Best regards, > Sergey Belyashov > > > пн, 27 апр. 2020 г., 19:29 Frank Ch. Eigler <[email protected]>: > >> Hi - >> >> > While analyzing code of CGEN I have found next code: >> > [...] >> > Can anybody add support for non-fixed-length ISAs? >> >> I am not expecting major cgen improvements. However, if your >> base-insn-size is large enough to contain all the opcode-like >> bits of your largest possible instruction, you may not need >> those improvements. >> >> - FChE >> >>