Re: re-building cgen-generated files in GNU binutils
Jan Beulich via Cgen <[email protected]> Fri, 2 Aug 2024 09:39:29 +0200
| Newsgroups | gmane.comp.tools.cgen.devel |
|---|---|
| Message-ID | <[email protected]> |
On 01.08.2024 17:26, Jose E. Marchesi wrote:
>> I was trying to double check a change of mine [1] by actually re-
>> generating the various output files, rather than manually applying the
>> opcodes/cgen-asm.in change to all respective files. However, using
>> guile 2.0.14 with cgen 1.1 sources fails on one of the first few lines
>> in cgen/guild.scm. Presumably the two versions don't fit together. I
>> wasn't able to find any newer cgen sources, though. May I ask for
>> hints / directions towards how to accomplish the goal of re-creating
>> those generated files under opcodes/ in the GNU binutils source tree?
>
> Try with guile 1.8.8.
>
> There has been steps done to get CGEN working with guile > 1, but I
> don't think CGEN master is ready yet.
Okay, I appear to have some success with guile 1.8.5, which I have
readily available on one of my systems. However, starting simple and
doing the re-gen for just cris, there are quite a few differences
(reproduced for reference at the bottom). I can see that the cris
files were last re-generated in 2021 and others in a batch in 2017.
Alan - what cgen version(s) did you use back then, in case you
recall? It doesn't look like it was 1.1 (yet as indicated in the
original mail still quoted above, I couldn't find any newer released
version there).
I further have no idea whether the guile version used may also matter
for the resulting output.
In addition I found it necessary to re-add the -s options in cgen.sh
that Tom's commit fd669f71eaf7 removed about a year ago. Is that kind
of an indication that the only valid way to re-gen is with the tip of
the dev tree of cgen, wherever that lives? If so, wouldn't there be a
need to re-gen more regularly, as surely changes made there will
affect output every once in a while?
Jan
--- a/opcodes/cris-desc.c
+++ b/opcodes/cris-desc.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@@ -25,7 +25,6 @@ This file is part of the GNU Binutils an
#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
-#include <stdlib.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
@@ -701,7 +700,11 @@ CGEN_KEYWORD cris_cgen_opval_h_supr =
/* The hardware table. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
+#else
+#define A(a) (1 << CGEN_HW_/**/a)
+#endif
const CGEN_HW_ENTRY cris_cgen_hw_table[] =
{
@@ -710,25 +713,25 @@ const CGEN_HW_ENTRY cris_cgen_hw_table[]
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } },
- { "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-inc", HW_H_INC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_inc, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-ccode", HW_H_CCODE, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_ccode, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-swap", HW_H_SWAP, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_swap, { 0, { { { (1<<MACH_BASE), 0 } } } } },
+ { "h-flagbits", HW_H_FLAGBITS, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_h_flagbits, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-v32-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-v32-non-v32", HW_H_V32, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
{ "h-gr", HW_H_GR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
- { "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
+ { "h-gr-pc", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
+ { "h-gr-real-pc", HW_H_GR_REAL_PC, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_pcreg, { 0, { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
{ "h-raw-gr-pc", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV0)|(1<<MACH_CRISV3)|(1<<MACH_CRISV8)|(1<<MACH_CRISV10), 0 } } } } },
- { "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
+ { "h-gr-acr", HW_H_GR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_gr_names_acr, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-raw-gr-acr", HW_H_RAW_GR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-sr", HW_H_SR, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
- { "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } },
- { "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } },
- { "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } },
- { "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
- { "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
+ { "h-sr-v0", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV0), 0 } } } } },
+ { "h-sr-v3", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV3), 0 } } } } },
+ { "h-sr-v8", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV8), 0 } } } } },
+ { "h-sr-v10", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v10, { 0, { { { (1<<MACH_CRISV10), 0 } } } } },
+ { "h-sr-v32", HW_H_SR_X, CGEN_ASM_KEYWORD, (PTR) & cris_cgen_opval_p_names_v32, { 0, { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-supr", HW_H_SUPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_CRISV32), 0 } } } } },
{ "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
{ "h-cbit-move", HW_H_CBIT_MOVE, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
@@ -773,7 +776,11 @@ const CGEN_HW_ENTRY cris_cgen_hw_table[]
/* The instruction field table. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
+#else
+#define A(a) (1 << CGEN_IFLD_/**/a)
+#endif
const CGEN_IFLD cris_cgen_ifld_table[] =
{
@@ -820,199 +827,207 @@ const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DSTSRC_MULTI_IFIELD [] =
{
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
- { 0, { 0 } }
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
+ { 0, { (const PTR) 0 } }
};
const CGEN_MAYBE_MULTI_IFLD CRIS_F_DISP9_MULTI_IFIELD [] =
{
- { 0, { &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
- { 0, { &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
- { 0, { 0 } }
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_HI] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_DISP9_LO] } },
+ { 0, { (const PTR) 0 } }
};
/* The operand table. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
+#else
+#define A(a) (1 << CGEN_OPERAND_/**/a)
+#endif
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) CRIS_OPERAND_##op
+#else
+#define OPERAND(op) CRIS_OPERAND_/**/op
+#endif
const CGEN_OPERAND cris_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", CRIS_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { &cris_cgen_ifld_table[CRIS_F_NIL] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_NIL] } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit: */
{ "cbit", CRIS_OPERAND_CBIT, HW_H_CBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* cbit-move: cbit for pre-V32, nothing for newer */
{ "cbit-move", CRIS_OPERAND_CBIT_MOVE, HW_H_CBIT_MOVE, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit: */
{ "vbit", CRIS_OPERAND_VBIT, HW_H_VBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* vbit-move: vbit for pre-V32, nothing for newer */
{ "vbit-move", CRIS_OPERAND_VBIT_MOVE, HW_H_VBIT_MOVE, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit: */
{ "zbit", CRIS_OPERAND_ZBIT, HW_H_ZBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* zbit-move: zbit for pre-V32, nothing for newer */
{ "zbit-move", CRIS_OPERAND_ZBIT_MOVE, HW_H_ZBIT_MOVE, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit: */
{ "nbit", CRIS_OPERAND_NBIT, HW_H_NBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* nbit-move: nbit for pre-V32, nothing for newer */
{ "nbit-move", CRIS_OPERAND_NBIT_MOVE, HW_H_NBIT_MOVE, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* xbit: */
{ "xbit", CRIS_OPERAND_XBIT, HW_H_XBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ibit: */
{ "ibit", CRIS_OPERAND_IBIT, HW_H_IBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* ubit: */
{ "ubit", CRIS_OPERAND_UBIT, HW_H_UBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
/* pbit: */
{ "pbit", CRIS_OPERAND_PBIT, HW_H_PBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV10)|(1<<MACH_CRISV32), 0 } } } } },
/* rbit: carry bit for MCP+restore-P flag bit */
{ "rbit", CRIS_OPERAND_RBIT, HW_H_RBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* sbit: */
{ "sbit", CRIS_OPERAND_SBIT, HW_H_SBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* mbit: */
{ "mbit", CRIS_OPERAND_MBIT, HW_H_MBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* qbit: */
{ "qbit", CRIS_OPERAND_QBIT, HW_H_QBIT, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_CRISV32), 0 } } } } },
/* prefix-set: Instruction-prefixed flag */
{ "prefix-set", CRIS_OPERAND_PREFIX_SET, HW_H_INSN_PREFIXED_P, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* prefixreg: Prefix address */
{ "prefixreg", CRIS_OPERAND_PREFIXREG, HW_H_PREFIXREG, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } } },
/* Rs: Source general register */
{ "Rs", CRIS_OPERAND_RS, HW_H_GR, 3, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND1] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* inc: Incrementness of indirect operand */
{ "inc", CRIS_OPERAND_INC, HW_H_INC, 10, 1,
- { 0, { &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_MEMMODE] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ps: Source special register */
{ "Ps", CRIS_OPERAND_PS, HW_H_SR, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* Ss: Source support register */
{ "Ss", CRIS_OPERAND_SS, HW_H_SUPR, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_CRISV32), 0 } } } } },
/* Sd: Destination support register */
{ "Sd", CRIS_OPERAND_SD, HW_H_SUPR, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_CRISV32), 0 } } } } },
/* i: Quick signed 6-bit */
{ "i", CRIS_OPERAND_I, HW_H_SINT, 5, 6,
- { 0, { &cris_cgen_ifld_table[CRIS_F_S6] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S6] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* j: Quick unsigned 6-bit */
{ "j", CRIS_OPERAND_J, HW_H_UINT, 5, 6,
- { 0, { &cris_cgen_ifld_table[CRIS_F_U6] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U6] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* c: Quick unsigned 5-bit */
{ "c", CRIS_OPERAND_C, HW_H_UINT, 4, 5,
- { 0, { &cris_cgen_ifld_table[CRIS_F_U5] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U5] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* qo: Quick unsigned 4-bit, PC-relative */
{ "qo", CRIS_OPERAND_QO, HW_H_ADDR, 3, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_QO] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_QO] } },
{ 0|A(PCREL_ADDR), { { { (1<<MACH_CRISV32), 0 } } } } },
/* Rd: Destination general register */
{ "Rd", CRIS_OPERAND_RD, HW_H_GR, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* sconst8: Signed byte [PC+] */
{ "sconst8", CRIS_OPERAND_SCONST8, HW_H_SINT, 15, 16,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* uconst8: Unsigned byte [PC+] */
{ "uconst8", CRIS_OPERAND_UCONST8, HW_H_UINT, 15, 16,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__BYTE] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* sconst16: Signed word [PC+] */
{ "sconst16", CRIS_OPERAND_SCONST16, HW_H_SINT, 15, 16,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* uconst16: Unsigned word [PC+] */
{ "uconst16", CRIS_OPERAND_UCONST16, HW_H_UINT, 15, 16,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* const32: Dword [PC+] */
{ "const32", CRIS_OPERAND_CONST32, HW_H_UINT, 31, 32,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD] } },
{ 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
/* const32-pcrel: Dword [PC+] */
{ "const32-pcrel", CRIS_OPERAND_CONST32_PCREL, HW_H_ADDR, 31, 32,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__DWORD_PCREL] } },
{ 0|A(PCREL_ADDR)|A(SIGN_OPT), { { { (1<<MACH_CRISV32), 0 } } } } },
/* Pd: Destination special register */
{ "Pd", CRIS_OPERAND_PD, HW_H_SR, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* o: Signed 8-bit */
{ "o", CRIS_OPERAND_O, HW_H_SINT, 7, 8,
- { 0, { &cris_cgen_ifld_table[CRIS_F_S8] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_S8] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* o-pcrel: 9-bit signed immediate PC-rel */
{ "o-pcrel", CRIS_OPERAND_O_PCREL, HW_H_IADDR, 0, 8,
- { 2, { &CRIS_F_DISP9_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &CRIS_F_DISP9_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* o-word-pcrel: 16-bit signed immediate PC-rel */
{ "o-word-pcrel", CRIS_OPERAND_O_WORD_PCREL, HW_H_IADDR, 15, 16,
- { 0, { &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_INDIR_PC__WORD_PCREL] } },
{ 0|A(SIGN_OPT)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
/* cc: Condition codes */
{ "cc", CRIS_OPERAND_CC, HW_H_CCODE, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* n: Quick unsigned 4-bit */
{ "n", CRIS_OPERAND_N, HW_H_UINT, 3, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_U4] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_U4] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* swapoption: Swap option */
{ "swapoption", CRIS_OPERAND_SWAPOPTION, HW_H_SWAP, 15, 4,
- { 0, { &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
+ { 0, { (const PTR) &cris_cgen_ifld_table[CRIS_F_OPERAND2] } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } },
/* list-of-flags: Flag bits as operand */
{ "list-of-flags", CRIS_OPERAND_LIST_OF_FLAGS, HW_H_FLAGBITS, 3, 8,
- { 2, { &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
+ { 2, { (const PTR) &CRIS_F_DSTSRC_MULTI_IFIELD[0] } },
{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
- { 0, { 0 } },
+ { 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } } } } }
};
@@ -1022,7 +1037,11 @@ const CGEN_OPERAND cris_cgen_operand_tab
/* The instruction table. */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
+#else
+#define A(a) (1 << CGEN_INSN_/**/a)
+#endif
static const CGEN_IBASE cris_cgen_insn_table[MAX_INSNS] =
{
@@ -2452,11 +2471,6 @@ init_tables (void)
{
}
-#ifndef opcodes_error_handler
-#define opcodes_error_handler(...) \
- fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
-#endif
-
static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
static void build_hw_table (CGEN_CPU_TABLE *);
static void build_ifield_table (CGEN_CPU_TABLE *);
@@ -2475,7 +2489,7 @@ lookup_mach_via_bfd_name (const CGEN_MAC
return table;
++table;
}
- return NULL;
+ abort ();
}
/* Subroutine of cris_cgen_cpu_open to build the hardware table. */
@@ -2617,11 +2631,8 @@ cris_cgen_rebuild_tables (CGEN_CPU_TABLE
{
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
{
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: cris_cgen_rebuild_tables: "
- "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
- cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
+ fprintf (stderr, "cris_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
+ cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
abort ();
}
@@ -2652,11 +2663,14 @@ cris_cgen_rebuild_tables (CGEN_CPU_TABLE
CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
CGEN_CPU_OPEN_ENDIAN: specify endian choice
- CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
CGEN_CPU_OPEN_END: terminates arguments
??? Simultaneous multiple isas might not make sense, but it's not (yet)
- precluded. */
+ precluded.
+
+ ??? We only support ISO C stdargs here, not K&R.
+ Laziness, plus experiment to see if anything requires K&R - eventually
+ K&R will no longer be supported - e.g. GDB is currently trying this. */
CGEN_CPU_DESC
cris_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
@@ -2666,7 +2680,6 @@ cris_cgen_cpu_open (enum cgen_cpu_open_a
CGEN_BITSET *isas = 0; /* 0 = "unspecified" */
unsigned int machs = 0; /* 0 = "unspecified" */
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
- enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
va_list ap;
if (! init_p)
@@ -2694,22 +2707,15 @@ cris_cgen_cpu_open (enum cgen_cpu_open_a
const CGEN_MACH *mach =
lookup_mach_via_bfd_name (cris_cgen_mach_table, name);
- if (mach != NULL)
- machs |= 1 << mach->num;
+ machs |= 1 << mach->num;
break;
}
case CGEN_CPU_OPEN_ENDIAN :
endian = va_arg (ap, enum cgen_endian);
break;
- case CGEN_CPU_OPEN_INSN_ENDIAN :
- insn_endian = va_arg (ap, enum cgen_endian);
- break;
default :
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: cris_cgen_cpu_open: "
- "unsupported argument `%d'"),
- arg_type);
+ fprintf (stderr, "cris_cgen_cpu_open: unsupported argument `%d'\n",
+ arg_type);
abort (); /* ??? return NULL? */
}
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
@@ -2724,17 +2730,18 @@ cris_cgen_cpu_open (enum cgen_cpu_open_a
if (endian == CGEN_ENDIAN_UNKNOWN)
{
/* ??? If target has only one, could have a default. */
- opcodes_error_handler
- (/* xgettext:c-format */
- _("internal error: cris_cgen_cpu_open: no endianness specified"));
+ fprintf (stderr, "cris_cgen_cpu_open: no endianness specified\n");
abort ();
}
cd->isas = cgen_bitset_copy (isas);
cd->machs = machs;
cd->endian = endian;
- cd->insn_endian
- = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
+ /* FIXME: for the sparc case we can determine insn-endianness statically.
+ The worry here is where both data and insn endian can be independently
+ chosen, in which case this function will need another argument.
+ Actually, will want to allow for more arguments in the future anyway. */
+ cd->insn_endian = endian;
/* Table (re)builder. */
cd->rebuild_tables = cris_cgen_rebuild_tables;
@@ -2784,10 +2791,18 @@ cris_cgen_cpu_close (CGEN_CPU_DESC cd)
regfree (CGEN_INSN_RX (insns));
}
- free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
- free ((CGEN_INSN *) cd->insn_table.init_entries);
- free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
- free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
free (cd);
}
--- a/opcodes/cris-desc.h
+++ b/opcodes/cris-desc.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@@ -25,14 +25,16 @@ This file is part of the GNU Binutils an
#ifndef CRIS_CPU_H
#define CRIS_CPU_H
-#ifdef __cplusplus
-extern "C" {
-#endif
+#include "opcode/cgen-bitset.h"
#define CGEN_ARCH cris
/* Given symbol S, return cris_cgen_<S>. */
+#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define CGEN_SYM(s) cris##_cgen_##s
+#else
+#define CGEN_SYM(s) cris/**/_cgen_/**/s
+#endif
/* Selected cpu families. */
@@ -235,12 +237,12 @@ typedef enum cgen_ifld_attr {
/* cgen_ifld attribute accessor macros. */
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_RESERVED)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_IFLD_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
/* Enum declaration for cris ifield types. */
typedef enum ifield_type {
@@ -268,10 +270,10 @@ typedef enum cgen_hw_attr {
/* cgen_hw attribute accessor macros. */
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_CACHE_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PC)) != 0)
-#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_HW_PROFILE)) != 0)
+#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
+#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
/* Enum declaration for cris hardware types. */
typedef enum cgen_hw_type {
@@ -305,14 +307,14 @@ typedef enum cgen_operand_attr {
/* cgen_operand attribute accessor macros. */
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SIGNED)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_RELAX)) != 0)
-#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
+#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
/* Enum declaration for cris operand types. */
typedef enum cgen_operand_type {
@@ -350,16 +352,16 @@ typedef enum cgen_insn_attr {
/* cgen_insn attribute accessor macros. */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
-#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_ALIAS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_VIRTUAL)) != 0)
-#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_COND_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_SKIP_CTI)) != 0)
-#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXABLE)) != 0)
-#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_RELAXED)) != 0)
-#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_NO_DIS)) != 0)
-#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool_ & (1 << CGEN_INSN_PBB)) != 0)
+#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
+#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
+#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
+#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
+#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
+#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
@@ -392,8 +394,4 @@ extern const CGEN_HW_ENTRY cris_cgen_hw_
- #ifdef __cplusplus
- }
- #endif
-
#endif /* CRIS_CPU_H */
--- a/opcodes/cris-opc.h
+++ b/opcodes/cris-opc.h
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright (C) 1996-2024 Free Software Foundation, Inc.
+Copyright 1996-2009 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@@ -25,10 +25,6 @@ This file is part of the GNU Binutils an
#ifndef CRIS_OPC_H
#define CRIS_OPC_H
-#ifdef __cplusplus
-extern "C" {
-#endif
-
/* Enum declaration for cris instruction types. */
typedef enum cgen_insn_type {
CRIS_INSN_INVALID, CRIS_INSN_NOP, CRIS_INSN_MOVE_B_R, CRIS_INSN_MOVE_W_R
@@ -156,8 +152,4 @@ struct cgen_fields
}
- #ifdef __cplusplus
- }
- #endif
-
#endif /* CRIS_OPC_H */