[PATCH v2] drm/rockchip: vop2: give rk3576 VP2 a primary plane

On rk3576 the two Cluster windows are the only windows typed
DRM_PLANE_TYPE_PRIMARY, and both have possible_vp_mask = BIT(0) | BIT(1),
so they can only be attached to VP0 or VP1. VP2's only attachable
windows are the Esmart windows, which are all DRM_PLANE_TYPE_OVERLAY.

vop2_create_crtcs() requires every video port a board wires up (an output
endpoint on video_portN) to own a DRM_PLANE_TYPE_PRIMARY plane. On a
board whose DT routes any interface to VP2, no attachable primary plane
is found and probe fails with -ENOENT ("no primary plane for vp 2"),
tearing down the whole VOP2.

Promote Esmart0 to DRM_PLANE_TYPE_PRIMARY. Its possible_vp_mask is
BIT(0) | BIT(2); since vop2_create_crtcs() assigns primaries in window
array order and Cluster0/Cluster1 precede Esmart0, VP0 and VP1 still take
Cluster0/Cluster1, and only VP2 gains Esmart0 as its primary:

  VP0: primary Cluster0
  VP1: primary Cluster1
  VP2: primary Esmart0

Tested on Anbernic RG Vita Pro (rk3576), which routes its DP output to
VP2.

Signed-off-by: Tomonori Nakagawa <[email protected]>
---
v2: reword the commit message per Chaoyi Chen's review - VP2 is not
    DP-specific; describe the plane topology instead (the two
    PRIMARY-typed Cluster windows are limited to VP0/VP1 by
    possible_vp_mask, so VP2 has no attachable primary). No functional
    change.

 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
index 17eda592b..e7d013dc3 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
@@ -894,7 +894,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
 		.format_modifiers = format_modifiers,
 		.layer_sel_id = { 2, 0xf, 0, 0xf },
 		.supported_rotations = DRM_MODE_REFLECT_Y,
-		.type = DRM_PLANE_TYPE_OVERLAY,
+		.type = DRM_PLANE_TYPE_PRIMARY,
 		.axi_bus_id = 0,
 		.axi_yrgb_r_id = 0x10,
 		.axi_uv_r_id = 0x11,
-- 
2.54.0