drm: Branch 'master' - 8 commits
[email protected] (Alex Deucher)
| Newsgroups | gmane.comp.video.dri.patches |
|---|---|
| Message-ID | <[email protected]> |
amdgpu/amdgpu_cs.c | 8 + amdgpu/amdgpu_internal.h | 1 tests/amdgpu/basic_tests.c | 284 +++++++++++++++++++++++++++++++++++++-------- 3 files changed, 246 insertions(+), 47 deletions(-) New commits: commit f884af9b57ff480d3c87870d8b40055d9c8c6cfe Author: Ken Wang <[email protected]> Date: Thu Feb 4 13:52:22 2016 +0800 amdgpu: fix for submition with no ibs Avoid a crash if no IBs are specified. Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index b4f41b0..fb5b3a8 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -190,6 +190,10 @@ static int amdgpu_cs_submit_one(amdgpu_context_handle context, return -EINVAL; if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT) return -EINVAL; + if (ibs_request->number_of_ibs == 0) { + ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ; + return 0; + } user_fence = (ibs_request->fence_info.handle != NULL); size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1; @@ -422,6 +426,10 @@ int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence, return -EINVAL; if (fence->ring >= AMDGPU_CS_MAX_RINGS) return -EINVAL; + if (fence->fence == AMDGPU_NULL_SUBMIT_SEQ) { + *expired = true; + return 0; + } *expired = false; diff --git a/amdgpu/amdgpu_internal.h b/amdgpu/amdgpu_internal.h index 557ba1f..4f039b6 100644 --- a/amdgpu/amdgpu_internal.h +++ b/amdgpu/amdgpu_internal.h @@ -44,6 +44,7 @@ #define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y)) #define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff +#define AMDGPU_NULL_SUBMIT_SEQ 0 struct amdgpu_bo_va_hole { struct list_head list; commit 6950af4e8475fa969ba46675fe2665c842fc4b79 Author: Alex Deucher <[email protected]> Date: Wed Feb 3 18:59:33 2016 -0500 tests/amdgpu: add a test for cp dma copy Use the CP to copy data between buffers Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 5a02ab5..4ef6014 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -455,12 +455,19 @@ static void amdgpu_command_submission_cp_const_fill(void) amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_GFX); } +static void amdgpu_command_submission_cp_copy_data(void) +{ + amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_GFX); +} + static void amdgpu_command_submission_gfx(void) { /* write data using the CP */ amdgpu_command_submission_cp_write_data(); /* const fill using the CP */ amdgpu_command_submission_cp_const_fill(); + /* copy data using the CP */ + amdgpu_command_submission_cp_copy_data(); /* separate IB buffers for multi-IB submission */ amdgpu_command_submission_gfx_separate_ibs(); /* shared IB buffer for multi-IB submission */ @@ -1023,6 +1030,17 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; pm4[i++] = 0xffffffff & bo2_mc; pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + } else if (ip_type == AMDGPU_HW_IP_GFX) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(0) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = sdma_write_length; } amdgpu_test_exec_cs_helper(context_handle, commit 35c35ea66d7940e78cf375e569e659f66e9fb69d Author: Alex Deucher <[email protected]> Date: Wed Feb 3 18:55:20 2016 -0500 tests/amdgpu: make amdgpu_command_submission_sdma_copy_linear generic So it can be shared for CP tests. Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index a116154..5a02ab5 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -51,6 +51,7 @@ static void amdgpu_semaphore_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); +static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type); CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, @@ -949,7 +950,7 @@ static void amdgpu_command_submission_sdma_const_fill(void) amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_DMA); } -static void amdgpu_command_submission_sdma_copy_linear(void) +static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) { const int sdma_write_length = 1024; const int pm4_dw = 256; @@ -1014,17 +1015,18 @@ static void amdgpu_command_submission_sdma_copy_linear(void) /* fullfill PM4: test DMA copy linear */ i = j = 0; - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - pm4[i++] = sdma_write_length; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - + if (ip_type == AMDGPU_HW_IP_DMA) { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); + pm4[i++] = sdma_write_length; + pm4[i++] = 0; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + } amdgpu_test_exec_cs_helper(context_handle, - AMDGPU_HW_IP_DMA, 0, + ip_type, 0, i, pm4, 2, resources, ib_info, ibs_request); @@ -1055,6 +1057,11 @@ static void amdgpu_command_submission_sdma_copy_linear(void) CU_ASSERT_EQUAL(r, 0); } +static void amdgpu_command_submission_sdma_copy_linear(void) +{ + amdgpu_command_submission_copy_linear_helper(AMDGPU_HW_IP_DMA); +} + static void amdgpu_command_submission_sdma(void) { amdgpu_command_submission_sdma_write_linear(); commit 0edc442560c792f9dc1acdc51c0c1a3b586f38d9 Author: Alex Deucher <[email protected]> Date: Wed Feb 3 18:52:18 2016 -0500 tests/amdgpu: add a test for cp dma fill Use the CP to fill to memory. Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 3e54787..a116154 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -449,10 +449,17 @@ static void amdgpu_command_submission_cp_write_data(void) amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_GFX); } +static void amdgpu_command_submission_cp_const_fill(void) +{ + amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_GFX); +} + static void amdgpu_command_submission_gfx(void) { /* write data using the CP */ amdgpu_command_submission_cp_write_data(); + /* const fill using the CP */ + amdgpu_command_submission_cp_const_fill(); /* separate IB buffers for multi-IB submission */ amdgpu_command_submission_gfx_separate_ibs(); /* shared IB buffer for multi-IB submission */ @@ -896,6 +903,17 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; pm4[i++] = 0xdeadbeaf; pm4[i++] = sdma_write_length; + } else if (ip_type == AMDGPU_HW_IP_GFX) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(2) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; } amdgpu_test_exec_cs_helper(context_handle, commit 7c656ba72fb9f004c2bd6b578fe68966d9ef9118 Author: Alex Deucher <[email protected]> Date: Wed Feb 3 18:38:50 2016 -0500 tests/amdgpu: make amdgpu_command_submission_sdma_const_fill generic So it can be shared for CP tests. Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index dbfcfff..3e54787 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -50,6 +50,7 @@ static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); +static void amdgpu_command_submission_const_fill_helper(unsigned ip_type); CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, @@ -839,7 +840,7 @@ static void amdgpu_command_submission_sdma_write_linear(void) amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA); } -static void amdgpu_command_submission_sdma_const_fill(void) +static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) { const int sdma_write_length = 1024 * 1024; const int pm4_dw = 256; @@ -888,15 +889,17 @@ static void amdgpu_command_submission_sdma_const_fill(void) /* fullfill PM4: test DMA const fill */ i = j = 0; - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, - SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = sdma_write_length; + if (ip_type == AMDGPU_HW_IP_DMA) { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, + SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = sdma_write_length; + } amdgpu_test_exec_cs_helper(context_handle, - AMDGPU_HW_IP_DMA, 0, + ip_type, 0, i, pm4, 1, resources, ib_info, ibs_request); @@ -923,6 +926,11 @@ static void amdgpu_command_submission_sdma_const_fill(void) CU_ASSERT_EQUAL(r, 0); } +static void amdgpu_command_submission_sdma_const_fill(void) +{ + amdgpu_command_submission_const_fill_helper(AMDGPU_HW_IP_DMA); +} + static void amdgpu_command_submission_sdma_copy_linear(void) { const int sdma_write_length = 1024; commit 47c7e7a6dd92c7c60c899b7103cf2a4457f83936 Author: Alex Deucher <[email protected]> Date: Wed Feb 3 18:33:45 2016 -0500 tests/amdgpu: add a test for cp write data Use the CP to write data to memory. Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 6f238bc..dbfcfff 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -84,6 +84,117 @@ CU_TestInfo basic_tests[] = { #define GFX_COMPUTE_NOP 0xffff1000 #define SDMA_NOP 0x0 +/* PM4 */ +#define PACKET_TYPE0 0 +#define PACKET_TYPE1 1 +#define PACKET_TYPE2 2 +#define PACKET_TYPE3 3 + +#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) +#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) +#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) +#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) +#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ + ((reg) & 0xFFFF) | \ + ((n) & 0x3FFF) << 16) +#define CP_PACKET2 0x80000000 +#define PACKET2_PAD_SHIFT 0 +#define PACKET2_PAD_MASK (0x3fffffff << 0) + +#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) + +#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ + (((op) & 0xFF) << 8) | \ + ((n) & 0x3FFF) << 16) + +/* Packet 3 types */ +#define PACKET3_NOP 0x10 + +#define PACKET3_WRITE_DATA 0x37 +#define WRITE_DATA_DST_SEL(x) ((x) << 8) + /* 0 - register + * 1 - memory (sync - via GRBM) + * 2 - gl2 + * 3 - gds + * 4 - reserved + * 5 - memory (async - direct) + */ +#define WR_ONE_ADDR (1 << 16) +#define WR_CONFIRM (1 << 20) +#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + */ +#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) + /* 0 - me + * 1 - pfp + * 2 - ce + */ + +#define PACKET3_DMA_DATA 0x50 +/* 1. header + * 2. CONTROL + * 3. SRC_ADDR_LO or DATA [31:0] + * 4. SRC_ADDR_HI [31:0] + * 5. DST_ADDR_LO [31:0] + * 6. DST_ADDR_HI [7:0] + * 7. COMMAND [30:21] | BYTE_COUNT [20:0] + */ +/* CONTROL */ +# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) + /* 0 - ME + * 1 - PFP + */ +# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) +# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) + /* 0 - DST_ADDR using DAS + * 1 - GDS + * 3 - DST_ADDR using L2 + */ +# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) + /* 0 - LRU + * 1 - Stream + * 2 - Bypass + */ +# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) +# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) + /* 0 - SRC_ADDR using SAS + * 1 - GDS + * 2 - DATA + * 3 - SRC_ADDR using L2 + */ +# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) +/* COMMAND */ +# define PACKET3_DMA_DATA_DIS_WC (1 << 21) +# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) + /* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) + /* 0 - none + * 1 - 8 in 16 + * 2 - 8 in 32 + * 3 - 8 in 64 + */ +# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) + /* 0 - memory + * 1 - register + */ +# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) +# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) +# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) + int suite_basic_tests_init(void) { int r; @@ -332,8 +443,15 @@ static void amdgpu_command_submission_gfx_shared_ib(void) CU_ASSERT_EQUAL(r, 0); } +static void amdgpu_command_submission_cp_write_data(void) +{ + amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_GFX); +} + static void amdgpu_command_submission_gfx(void) { + /* write data using the CP */ + amdgpu_command_submission_cp_write_data(); /* separate IB buffers for multi-IB submission */ amdgpu_command_submission_gfx_separate_ibs(); /* shared IB buffer for multi-IB submission */ @@ -679,6 +797,13 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) pm4[i++] = sdma_write_length; while(j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; + } else if (ip_type == AMDGPU_HW_IP_GFX) { + pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); + pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; } amdgpu_test_exec_cs_helper(context_handle, commit c5da5eade0b5769fce40f79fbad9153ea760b954 Author: Alex Deucher <[email protected]> Date: Thu Feb 4 12:23:43 2016 -0500 tests/amdgpu: make amdgpu_command_submission_sdma_write_linear generic So it can be shared for CP tests. Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index df5f5bc..6f238bc 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -49,6 +49,8 @@ static void amdgpu_command_submission_sdma(void); static void amdgpu_userptr_test(void); static void amdgpu_semaphore_test(void); +static void amdgpu_command_submission_write_linear_helper(unsigned ip_type); + CU_TestInfo basic_tests[] = { { "Query Info Test", amdgpu_query_info_test }, { "Memory alloc Test", amdgpu_memory_alloc }, @@ -619,7 +621,7 @@ static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, CU_ASSERT_EQUAL(r, 0); } -static void amdgpu_command_submission_sdma_write_linear(void) +static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) { const int sdma_write_length = 128; const int pm4_dw = 256; @@ -669,16 +671,18 @@ static void amdgpu_command_submission_sdma_write_linear(void) /* fullfill PM4: test DMA write-linear */ i = j = 0; - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; + if (ip_type == AMDGPU_HW_IP_DMA) { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + } amdgpu_test_exec_cs_helper(context_handle, - AMDGPU_HW_IP_DMA, 0, + ip_type, 0, i, pm4, 1, resources, ib_info, ibs_request); @@ -705,6 +709,11 @@ static void amdgpu_command_submission_sdma_write_linear(void) CU_ASSERT_EQUAL(r, 0); } +static void amdgpu_command_submission_sdma_write_linear(void) +{ + amdgpu_command_submission_write_linear_helper(AMDGPU_HW_IP_DMA); +} + static void amdgpu_command_submission_sdma_const_fill(void) { const int sdma_write_length = 1024 * 1024; commit 8be79be0433ba64c4674c3394b3fc8cbc33c46af Author: Alex Deucher <[email protected]> Date: Wed Feb 3 18:14:48 2016 -0500 tests/amdgpu: make amdgpu_sdma_test_exec_cs() generic (v2) Share with upcoming CP tests. v2: drop unnecessary forward declaration Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index fa0ed12..df5f5bc 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -542,11 +542,12 @@ static void amdgpu_command_submission_compute(void) * pm4_src, resources, ib_info, and ibs_request * submit command stream described in ibs_request and wait for this IB accomplished */ -static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle, - int instance, int pm4_dw, uint32_t *pm4_src, - int res_cnt, amdgpu_bo_handle *resources, - struct amdgpu_cs_ib_info *ib_info, - struct amdgpu_cs_request *ibs_request) +static void amdgpu_test_exec_cs_helper(amdgpu_context_handle context_handle, + unsigned ip_type, + int instance, int pm4_dw, uint32_t *pm4_src, + int res_cnt, amdgpu_bo_handle *resources, + struct amdgpu_cs_ib_info *ib_info, + struct amdgpu_cs_request *ibs_request) { int r; uint32_t expired; @@ -579,7 +580,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle, ib_info->ib_mc_address = ib_result_mc_address; ib_info->size = pm4_dw; - ibs_request->ip_type = AMDGPU_HW_IP_DMA; + ibs_request->ip_type = ip_type; ibs_request->ring = instance; ibs_request->number_of_ibs = 1; ibs_request->ibs = ib_info; @@ -601,7 +602,7 @@ static void amdgpu_sdma_test_exec_cs(amdgpu_context_handle context_handle, r = amdgpu_bo_list_destroy(ibs_request->resources); CU_ASSERT_EQUAL(r, 0); - fence_status.ip_type = AMDGPU_HW_IP_DMA; + fence_status.ip_type = ip_type; fence_status.ring = ibs_request->ring; fence_status.context = context_handle; fence_status.fence = ibs_request->seq_no; @@ -676,10 +677,11 @@ static void amdgpu_command_submission_sdma_write_linear(void) while(j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; - amdgpu_sdma_test_exec_cs(context_handle, 0, - i, pm4, - 1, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + AMDGPU_HW_IP_DMA, 0, + i, pm4, + 1, resources, + ib_info, ibs_request); /* verify if SDMA test result meets with expected */ i = 0; @@ -759,10 +761,11 @@ static void amdgpu_command_submission_sdma_const_fill(void) pm4[i++] = 0xdeadbeaf; pm4[i++] = sdma_write_length; - amdgpu_sdma_test_exec_cs(context_handle, 0, - i, pm4, - 1, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + AMDGPU_HW_IP_DMA, 0, + i, pm4, + 1, resources, + ib_info, ibs_request); /* verify if SDMA test result meets with expected */ i = 0; @@ -860,10 +863,11 @@ static void amdgpu_command_submission_sdma_copy_linear(void) pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - amdgpu_sdma_test_exec_cs(context_handle, 0, - i, pm4, - 2, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + AMDGPU_HW_IP_DMA, 0, + i, pm4, + 2, resources, + ib_info, ibs_request); /* verify if SDMA test result meets with expected */ i = 0; @@ -954,10 +958,11 @@ static void amdgpu_userptr_test(void) while (j++ < sdma_write_length) pm4[i++] = 0xdeadbeaf; - amdgpu_sdma_test_exec_cs(context_handle, 0, - i, pm4, - 1, &handle, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + AMDGPU_HW_IP_DMA, 0, + i, pm4, + 1, &handle, + ib_info, ibs_request); i = 0; while (i < sdma_write_length) { CU_ASSERT_EQUAL(((int*)ptr)[i++], 0xdeadbeaf); ------------------------------------------------------------------------------ Site24x7 APM Insight: Get Deep Visibility into Application Performance APM + Mobile APM + RUM: Monitor 3 App instances at just $35/Month Monitor end-to-end web transactions and take corrective actions now Troubleshoot faster and improve end-user experience. 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