drm: Branch 'master' - 4 commits

[email protected] (Marek Ol????k)
Newsgroups gmane.comp.video.dri.patches
Message-ID <[email protected]> 
 amdgpu/amdgpu_gpu_info.c |   20 +++++++++++-------
 include/drm/amdgpu_drm.h |   42 +++++++++++++++++++++++---------------
 include/drm/radeon_drm.h |   51 ++++++++++++++++++++++++++++++++++++++---------
 radeon/radeon_surface.c  |    8 +++++++
 4 files changed, 88 insertions(+), 33 deletions(-)

New commits:
commit a625ba8d2d4da33bd6d7bb057d2bdf7cb484fd6c
Author: Ronie Salgado <[email protected]>
Date:   Wed Apr 13 21:56:15 2016 +0200

    amdgpu: add SI support
    
    v2: without the amdgpu_drm.h change
    
    Signed-off-by: Marek Olšák <[email protected]>

diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 3eecd79..0f23297 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -187,10 +187,12 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 		if (r)
 			return r;
 
-		r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
+		if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+			r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
 					     &dev->info.pa_sc_raster_cfg1[i]);
-		if (r)
-			return r;
+			if (r)
+				return r;
+		}
 	}
 
 	r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
@@ -198,10 +200,12 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 	if (r)
 		return r;
 
-	r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
-				     dev->info.gb_macro_tile_mode);
-	if (r)
-		return r;
+	if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+		r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
+					     dev->info.gb_macro_tile_mode);
+		if (r)
+			return r;
+	}
 
 	r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
 				     &dev->info.gb_addr_cfg);
commit c65377977597e1d3a317aa5022ac7d3bc0f6ff83
Author: Marek Olšák <[email protected]>
Date:   Wed Aug 17 19:09:38 2016 +0200

    amdgpu: fix valgrind warnings caused by amdgpu_query_firmware_version

diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 0cc17f1..3eecd79 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -119,7 +119,7 @@ int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
 				  uint32_t *version, uint32_t *feature)
 {
 	struct drm_amdgpu_info request;
-	struct drm_amdgpu_info_firmware firmware;
+	struct drm_amdgpu_info_firmware firmware = {};
 	int r;
 
 	memset(&request, 0, sizeof(request));
commit 77bc69ae9cb2a719ae5142b4b91e6dc657e4c119
Author: Marek Olšák <[email protected]>
Date:   Fri Aug 19 16:10:58 2016 +0200

    amdgpu: sync amdgpu_drm.h with the kernel
    
    Reviewed-by: Edward O'Callaghan <[email protected]>

diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index d43895e..d8f2497 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -34,6 +34,10 @@
 
 #include "drm.h"
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 #define DRM_AMDGPU_GEM_CREATE		0x00
 #define DRM_AMDGPU_GEM_MMAP		0x01
 #define DRM_AMDGPU_CTX			0x02
@@ -485,6 +489,22 @@ struct drm_amdgpu_cs_chunk_data {
 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT	8
 #define AMDGPU_INFO_MMR_SH_INDEX_MASK	0xff
 
+struct drm_amdgpu_query_fw {
+	/** AMDGPU_INFO_FW_* */
+	uint32_t fw_type;
+	/**
+	 * Index of the IP if there are more IPs of
+	 * the same type.
+	 */
+	uint32_t ip_instance;
+	/**
+	 * Index of the engine. Whether this is used depends
+	 * on the firmware type. (e.g. MEC, SDMA)
+	 */
+	uint32_t index;
+	uint32_t _pad;
+};
+
 /* Input structure for the INFO ioctl */
 struct drm_amdgpu_info {
 	/* Where the return value will be stored */
@@ -520,21 +540,7 @@ struct drm_amdgpu_info {
 			uint32_t flags;
 		} read_mmr_reg;
 
-		struct {
-			/** AMDGPU_INFO_FW_* */
-			uint32_t fw_type;
-			/**
-			 * Index of the IP if there are more IPs of
-			 * the same type.
-			 */
-			uint32_t ip_instance;
-			/**
-			 * Index of the engine. Whether this is used depends
-			 * on the firmware type. (e.g. MEC, SDMA)
-			 */
-			uint32_t index;
-			uint32_t _pad;
-		} query_fw;
+		struct drm_amdgpu_query_fw query_fw;
 	};
 };
 
@@ -642,6 +648,10 @@ struct drm_amdgpu_info_hw_ip {
 #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
 #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
 #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
-#define AMDGPU_FAMILY_CZ			135 /* Carrizo */
+#define AMDGPU_FAMILY_CZ			135 /* Carrizo, Stoney */
+
+#if defined(__cplusplus)
+}
+#endif
 
 #endif
commit 39fff5996227692cf8b6a75771a28a8d624f16ef
Author: Marek Olšák <[email protected]>
Date:   Fri Aug 19 16:07:50 2016 +0200

    radeon: sync radeon_drm.h with the kernel
    
    the CIK tile mode definitions are moved out,
    userspace doesn't use them
    
    Reviewed-by: Edward O'Callaghan <[email protected]>

diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index cd31794..f09cc04 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -35,6 +35,10 @@
 
 #include "drm.h"
 
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
 /* WARNING: If you change any of these defines, make sure to change the
  * defines in the X server file (radeon_sarea.h)
  */
@@ -511,6 +515,7 @@ typedef struct {
 #define DRM_RADEON_GEM_BUSY		0x2a
 #define DRM_RADEON_GEM_VA		0x2b
 #define DRM_RADEON_GEM_OP		0x2c
+#define DRM_RADEON_GEM_USERPTR		0x2d
 
 #define DRM_IOCTL_RADEON_CP_INIT    DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
 #define DRM_IOCTL_RADEON_CP_START   DRM_IO(  DRM_COMMAND_BASE + DRM_RADEON_CP_START)
@@ -554,6 +559,7 @@ typedef struct {
 #define DRM_IOCTL_RADEON_GEM_BUSY	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_BUSY, struct drm_radeon_gem_busy)
 #define DRM_IOCTL_RADEON_GEM_VA		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_VA, struct drm_radeon_gem_va)
 #define DRM_IOCTL_RADEON_GEM_OP		DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_OP, struct drm_radeon_gem_op)
+#define DRM_IOCTL_RADEON_GEM_USERPTR	DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_USERPTR, struct drm_radeon_gem_userptr)
 
 typedef struct drm_radeon_init {
 	enum {
@@ -796,7 +802,13 @@ struct drm_radeon_gem_info {
 	uint64_t	vram_visible;
 };
 
-#define RADEON_GEM_NO_BACKING_STORE 1
+#define RADEON_GEM_NO_BACKING_STORE	(1 << 0)
+#define RADEON_GEM_GTT_UC		(1 << 1)
+#define RADEON_GEM_GTT_WC		(1 << 2)
+/* BO is expected to be accessed by the CPU */
+#define RADEON_GEM_CPU_ACCESS		(1 << 3)
+/* CPU access is not expected to work for this BO */
+#define RADEON_GEM_NO_CPU_ACCESS	(1 << 4)
 
 struct drm_radeon_gem_create {
 	uint64_t	size;
@@ -806,6 +818,23 @@ struct drm_radeon_gem_create {
 	uint32_t	flags;
 };
 
+/*
+ * This is not a reliable API and you should expect it to fail for any
+ * number of reasons and have fallback path that do not use userptr to
+ * perform any operation.
+ */
+#define RADEON_GEM_USERPTR_READONLY	(1 << 0)
+#define RADEON_GEM_USERPTR_ANONONLY	(1 << 1)
+#define RADEON_GEM_USERPTR_VALIDATE	(1 << 2)
+#define RADEON_GEM_USERPTR_REGISTER	(1 << 3)
+
+struct drm_radeon_gem_userptr {
+	uint64_t		addr;
+	uint64_t		size;
+	uint32_t		flags;
+	uint32_t		handle;
+};
+
 #define RADEON_TILING_MACRO				0x1
 #define RADEON_TILING_MICRO				0x2
 #define RADEON_TILING_SWAP_16BIT			0x4
@@ -943,6 +972,7 @@ struct drm_radeon_cs_chunk {
 };
 
 /* drm_radeon_cs_reloc.flags */
+#define RADEON_RELOC_PRIO_MASK		(0xf << 0)
 
 struct drm_radeon_cs_reloc {
 	uint32_t		handle;
@@ -1008,7 +1038,13 @@ struct drm_radeon_cs {
 #define RADEON_INFO_NUM_BYTES_MOVED	0x1d
 #define RADEON_INFO_VRAM_USAGE		0x1e
 #define RADEON_INFO_GTT_USAGE		0x1f
-
+#define RADEON_INFO_ACTIVE_CU_COUNT	0x20
+#define RADEON_INFO_CURRENT_GPU_TEMP	0x21
+#define RADEON_INFO_CURRENT_GPU_SCLK	0x22
+#define RADEON_INFO_CURRENT_GPU_MCLK	0x23
+#define RADEON_INFO_READ_REG		0x24
+#define RADEON_INFO_VA_UNMAP_WORKING	0x25
+#define RADEON_INFO_GPU_RESET_COUNTER	0x26
 
 struct drm_radeon_info {
 	uint32_t		request;
@@ -1034,13 +1070,10 @@ struct drm_radeon_info {
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA	3
 #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA	2
 
-#define CIK_TILE_MODE_COLOR_2D			14
-#define CIK_TILE_MODE_COLOR_2D_SCANOUT		10
-#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64       0
-#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128      1
-#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256      2
-#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512      3
-#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4
 #define CIK_TILE_MODE_DEPTH_STENCIL_1D		5
 
+#if defined(__cplusplus)
+}
+#endif
+
 #endif
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index 1424660..16a8b00 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -42,6 +42,14 @@
 #include "radeon_drm.h"
 #include "radeon_surface.h"
 
+#define CIK_TILE_MODE_COLOR_2D			14
+#define CIK_TILE_MODE_COLOR_2D_SCANOUT		10
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_64       0
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_128      1
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_256      2
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_512      3
+#define CIK_TILE_MODE_DEPTH_STENCIL_2D_TILESPLIT_ROW_SIZE 4
+
 #define ALIGN(value, alignment) (((value) + alignment - 1) & ~(alignment - 1))
 #define MAX2(A, B)              ((A) > (B) ? (A) : (B))
 #define MIN2(A, B)              ((A) < (B) ? (A) : (B))

------------------------------------------------------------------------------

--
_______________________________________________
Dri-patches mailing list
[email protected]
https://lists.sourceforge.net/lists/listinfo/dri-patches
lmpx.com only provides a reader for public news (NNTP) servers. It is not affiliated with the servers or forums shown here and is not responsible for the content of articles, which is written by their respective authors.