drm: Branch 'master' - 3 commits
[email protected] (Alex Deucher) Fri, 12 Jan 2018 17:24:52 +0000 (UTC)
| Newsgroups | gmane.comp.video.dri.patches |
|---|---|
| Message-ID | <[email protected]> |
tests/amdgpu/basic_tests.c | 464 +++++++++++++++++++++++---------------------- 1 file changed, 242 insertions(+), 222 deletions(-) New commits: commit f115de819bc10bb36565f344a66fa619219911b9 Author: Hawking Zhang <[email protected]> Date: Mon Jan 8 11:20:30 2018 +0800 tests/amdgpu: execute copy linear on all the available rings Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 0a198e48..0f75e896 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -1114,9 +1114,10 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) struct amdgpu_cs_request *ibs_request; uint64_t bo1_mc, bo2_mc; volatile unsigned char *bo1_cpu, *bo2_cpu; - int i, j, r, loop1, loop2; + int i, j, r, loop1, loop2, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle bo1_va_handle, bo2_va_handle; + struct drm_amdgpu_info_hw_ip hw_ip_info; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -1127,6 +1128,9 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -1134,107 +1138,111 @@ static void amdgpu_command_submission_copy_linear_helper(unsigned ip_type) resources = calloc(2, sizeof(amdgpu_bo_handle)); CU_ASSERT_NOT_EQUAL(resources, NULL); - loop1 = loop2 = 0; - /* run 9 circle to test all mapping combination */ - while(loop1 < 2) { - while(loop2 < 2) { - /* allocate UC bo1for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop1], &bo1, - (void**)&bo1_cpu, &bo1_mc, - &bo1_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* set bo1 */ - memset((void*)bo1_cpu, 0xaa, sdma_write_length); - - /* allocate UC bo2 for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop2], &bo2, - (void**)&bo2_cpu, &bo2_mc, - &bo2_va_handle); - CU_ASSERT_EQUAL(r, 0); - - /* clear bo2 */ - memset((void*)bo2_cpu, 0, sdma_write_length); - - resources[0] = bo1; - resources[1] = bo2; - - /* fulfill PM4: test DMA copy linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, - sdma_write_length); - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else + for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { + loop1 = loop2 = 0; + /* run 9 circle to test all mapping combination */ + while(loop1 < 2) { + while(loop2 < 2) { + /* allocate UC bo1for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop1], &bo1, + (void**)&bo1_cpu, &bo1_mc, + &bo1_va_handle); + CU_ASSERT_EQUAL(r, 0); + + /* set bo1 */ + memset((void*)bo1_cpu, 0xaa, sdma_write_length); + + /* allocate UC bo2 for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop2], &bo2, + (void**)&bo2_cpu, &bo2_mc, + &bo2_va_handle); + CU_ASSERT_EQUAL(r, 0); + + /* clear bo2 */ + memset((void*)bo2_cpu, 0, sdma_write_length); + + resources[0] = bo1; + resources[1] = bo2; + + /* fulfill PM4: test DMA copy linear */ + i = j = 0; + if (ip_type == AMDGPU_HW_IP_DMA) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, + 0, 0, 0, + sdma_write_length); + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, + SDMA_COPY_SUB_OPCODE_LINEAR, + 0); + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + pm4[i++] = 0; + pm4[i++] = 0xffffffff & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xffffffff & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + } + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | + PACKET3_DMA_DATA_SI_DST_SEL(0) | + PACKET3_DMA_DATA_SI_SRC_SEL(0) | + PACKET3_DMA_DATA_SI_CP_SYNC | + (0xffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; pm4[i++] = sdma_write_length; - pm4[i++] = 0; - pm4[i++] = 0xffffffff & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xffffffff & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - } - - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | - PACKET3_DMA_DATA_SI_DST_SEL(0) | - PACKET3_DMA_DATA_SI_SRC_SEL(0) | - PACKET3_DMA_DATA_SI_CP_SYNC | - (0xffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; - } else { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(0) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xfffffffc & bo1_mc; - pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; - pm4[i++] = 0xfffffffc & bo2_mc; - pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; - pm4[i++] = sdma_write_length; + } else { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(0) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xfffffffc & bo1_mc; + pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; + pm4[i++] = 0xfffffffc & bo2_mc; + pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; + pm4[i++] = sdma_write_length; + } } - } - amdgpu_test_exec_cs_helper(context_handle, - ip_type, 0, - i, pm4, - 2, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + ip_type, ring_id, + i, pm4, + 2, resources, + ib_info, ibs_request); - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo2_cpu[i++], 0xaa); + } + r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + loop2++; } - r = amdgpu_bo_unmap_and_free(bo1, bo1_va_handle, bo1_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - r = amdgpu_bo_unmap_and_free(bo2, bo2_va_handle, bo2_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop2++; + loop1++; } - loop1++; } /* clean resources */ free(resources); commit cbbb8a332d972a4ab18622f1c53de21324735fef Author: Hawking Zhang <[email protected]> Date: Mon Jan 8 11:20:29 2018 +0800 tests/amdgpu: execute const fill on all the available rings Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 837ee9aa..0a198e48 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -981,9 +981,10 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) struct amdgpu_cs_request *ibs_request; uint64_t bo_mc; volatile uint32_t *bo_cpu; - int i, j, r, loop; + int i, j, r, loop, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; + struct drm_amdgpu_info_hw_ip hw_ip_info; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -994,6 +995,9 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -1001,83 +1005,86 @@ static void amdgpu_command_submission_const_fill_helper(unsigned ip_type) resources = calloc(1, sizeof(amdgpu_bo_handle)); CU_ASSERT_NOT_EQUAL(resources, NULL); - loop = 0; - while(loop < 2) { - /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length, 4096, - AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop], &bo, (void**)&bo_cpu, - &bo_mc, &va_handle); - CU_ASSERT_EQUAL(r, 0); + for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { + loop = 0; + while(loop < 2) { + /* allocate UC bo for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length, 4096, + AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop], &bo, (void**)&bo_cpu, + &bo_mc, &va_handle); + CU_ASSERT_EQUAL(r, 0); - /* clear bo */ - memset((void*)bo_cpu, 0, sdma_write_length); + /* clear bo */ + memset((void*)bo_cpu, 0, sdma_write_length); - resources[0] = bo; + resources[0] = bo; - /* fulfill PM4: test DMA const fill */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, 0, 0, 0, - sdma_write_length / 4); - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; - } else { - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, - SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = 0xdeadbeaf; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else + /* fulfill PM4: test DMA const fill */ + i = j = 0; + if (ip_type == AMDGPU_HW_IP_DMA) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_CONSTANT_FILL_SI, + 0, 0, 0, + sdma_write_length / 4); + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 16; + } else { + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_CONSTANT_FILL, 0, + SDMA_CONSTANT_FILL_EXTRA_SIZE(2)); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = 0xdeadbeaf; + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else + pm4[i++] = sdma_write_length; + } + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { + if (family_id == AMDGPU_FAMILY_SI) { + pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); + pm4[i++] = 0xdeadbeaf; + pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | + PACKET3_DMA_DATA_SI_DST_SEL(0) | + PACKET3_DMA_DATA_SI_SRC_SEL(2) | + PACKET3_DMA_DATA_SI_CP_SYNC; + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; pm4[i++] = sdma_write_length; + } else { + pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); + pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | + PACKET3_DMA_DATA_DST_SEL(0) | + PACKET3_DMA_DATA_SRC_SEL(2) | + PACKET3_DMA_DATA_CP_SYNC; + pm4[i++] = 0xdeadbeaf; + pm4[i++] = 0; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + pm4[i++] = sdma_write_length; + } } - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - if (family_id == AMDGPU_FAMILY_SI) { - pm4[i++] = PACKET3(PACKET3_DMA_DATA_SI, 4); - pm4[i++] = 0xdeadbeaf; - pm4[i++] = PACKET3_DMA_DATA_SI_ENGINE(0) | - PACKET3_DMA_DATA_SI_DST_SEL(0) | - PACKET3_DMA_DATA_SI_SRC_SEL(2) | - PACKET3_DMA_DATA_SI_CP_SYNC; - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - } else { - pm4[i++] = PACKET3(PACKET3_DMA_DATA, 5); - pm4[i++] = PACKET3_DMA_DATA_ENGINE(0) | - PACKET3_DMA_DATA_DST_SEL(0) | - PACKET3_DMA_DATA_SRC_SEL(2) | - PACKET3_DMA_DATA_CP_SYNC; - pm4[i++] = 0xdeadbeaf; - pm4[i++] = 0; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - pm4[i++] = sdma_write_length; - } - } - amdgpu_test_exec_cs_helper(context_handle, - ip_type, 0, - i, pm4, - 1, resources, - ib_info, ibs_request); + amdgpu_test_exec_cs_helper(context_handle, + ip_type, ring_id, + i, pm4, + 1, resources, + ib_info, ibs_request); - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < (sdma_write_length / 4)) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); - } + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < (sdma_write_length / 4)) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } - r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, - sdma_write_length); - CU_ASSERT_EQUAL(r, 0); - loop++; + r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, + sdma_write_length); + CU_ASSERT_EQUAL(r, 0); + loop++; + } } /* clean resources */ free(resources); commit 168dbe9a0ee29dbe5ddd16706147f2e6d8ad5576 Author: Hawking Zhang <[email protected]> Date: Mon Jan 8 11:20:28 2018 +0800 tests/amdgpu: execute write linear on all the available rings Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c index 9c918951..837ee9aa 100644 --- a/tests/amdgpu/basic_tests.c +++ b/tests/amdgpu/basic_tests.c @@ -868,9 +868,10 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) struct amdgpu_cs_request *ibs_request; uint64_t bo_mc; volatile uint32_t *bo_cpu; - int i, j, r, loop; + int i, j, r, loop, ring_id; uint64_t gtt_flags[2] = {0, AMDGPU_GEM_CREATE_CPU_GTT_USWC}; amdgpu_va_handle va_handle; + struct drm_amdgpu_info_hw_ip hw_ip_info; pm4 = calloc(pm4_dw, sizeof(*pm4)); CU_ASSERT_NOT_EQUAL(pm4, NULL); @@ -881,6 +882,9 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) ibs_request = calloc(1, sizeof(*ibs_request)); CU_ASSERT_NOT_EQUAL(ibs_request, NULL); + r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &hw_ip_info); + CU_ASSERT_EQUAL(r, 0); + r = amdgpu_cs_ctx_create(device_handle, &context_handle); CU_ASSERT_EQUAL(r, 0); @@ -888,65 +892,66 @@ static void amdgpu_command_submission_write_linear_helper(unsigned ip_type) resources = calloc(1, sizeof(amdgpu_bo_handle)); CU_ASSERT_NOT_EQUAL(resources, NULL); - loop = 0; - while(loop < 2) { - /* allocate UC bo for sDMA use */ - r = amdgpu_bo_alloc_and_map(device_handle, - sdma_write_length * sizeof(uint32_t), - 4096, AMDGPU_GEM_DOMAIN_GTT, - gtt_flags[loop], &bo, (void**)&bo_cpu, - &bo_mc, &va_handle); - CU_ASSERT_EQUAL(r, 0); + for (ring_id = 0; (1 << ring_id) & hw_ip_info.available_rings; ring_id++) { + loop = 0; + while(loop < 2) { + /* allocate UC bo for sDMA use */ + r = amdgpu_bo_alloc_and_map(device_handle, + sdma_write_length * sizeof(uint32_t), + 4096, AMDGPU_GEM_DOMAIN_GTT, + gtt_flags[loop], &bo, (void**)&bo_cpu, + &bo_mc, &va_handle); + CU_ASSERT_EQUAL(r, 0); - /* clear bo */ - memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); + /* clear bo */ + memset((void*)bo_cpu, 0, sdma_write_length * sizeof(uint32_t)); + resources[0] = bo; - resources[0] = bo; + /* fulfill PM4: test DMA write-linear */ + i = j = 0; + if (ip_type == AMDGPU_HW_IP_DMA) { + if (family_id == AMDGPU_FAMILY_SI) + pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, + sdma_write_length); + else + pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, + SDMA_WRITE_SUB_OPCODE_LINEAR, 0); + pm4[i++] = 0xffffffff & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + if (family_id >= AMDGPU_FAMILY_AI) + pm4[i++] = sdma_write_length - 1; + else if (family_id != AMDGPU_FAMILY_SI) + pm4[i++] = sdma_write_length; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + } else if ((ip_type == AMDGPU_HW_IP_GFX) || + (ip_type == AMDGPU_HW_IP_COMPUTE)) { + pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); + pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; + pm4[i++] = 0xfffffffc & bo_mc; + pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; + while(j++ < sdma_write_length) + pm4[i++] = 0xdeadbeaf; + } - /* fulfill PM4: test DMA write-linear */ - i = j = 0; - if (ip_type == AMDGPU_HW_IP_DMA) { - if (family_id == AMDGPU_FAMILY_SI) - pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_WRITE, 0, 0, 0, - sdma_write_length); - else - pm4[i++] = SDMA_PACKET(SDMA_OPCODE_WRITE, - SDMA_WRITE_SUB_OPCODE_LINEAR, 0); - pm4[i++] = 0xffffffff & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - if (family_id >= AMDGPU_FAMILY_AI) - pm4[i++] = sdma_write_length - 1; - else if (family_id != AMDGPU_FAMILY_SI) - pm4[i++] = sdma_write_length; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - } else if ((ip_type == AMDGPU_HW_IP_GFX) || - (ip_type == AMDGPU_HW_IP_COMPUTE)) { - pm4[i++] = PACKET3(PACKET3_WRITE_DATA, 2 + sdma_write_length); - pm4[i++] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM; - pm4[i++] = 0xfffffffc & bo_mc; - pm4[i++] = (0xffffffff00000000 & bo_mc) >> 32; - while(j++ < sdma_write_length) - pm4[i++] = 0xdeadbeaf; - } + amdgpu_test_exec_cs_helper(context_handle, + ip_type, ring_id, + i, pm4, + 1, resources, + ib_info, ibs_request); - amdgpu_test_exec_cs_helper(context_handle, - ip_type, 0, - i, pm4, - 1, resources, - ib_info, ibs_request); + /* verify if SDMA test result meets with expected */ + i = 0; + while(i < sdma_write_length) { + CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + } - /* verify if SDMA test result meets with expected */ - i = 0; - while(i < sdma_write_length) { - CU_ASSERT_EQUAL(bo_cpu[i++], 0xdeadbeaf); + r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, + sdma_write_length * sizeof(uint32_t)); + CU_ASSERT_EQUAL(r, 0); + loop++; } - - r = amdgpu_bo_unmap_and_free(bo, va_handle, bo_mc, - sdma_write_length * sizeof(uint32_t)); - CU_ASSERT_EQUAL(r, 0); - loop++; } /* clean resources */ free(resources); ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot -- _______________________________________________ Dri-patches mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-patches