drm: Branch 'master' - 2 commits
[email protected] (GitLab Mirror) Wed, 20 Jun 2018 23:41:06 +0000 (UTC)
| Newsgroups | gmane.comp.video.dri.patches |
|---|---|
| Message-ID | <[email protected]> |
intel/intel_chipset.h | 42 +++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 19 deletions(-) New commits: commit 7164abebecfbf450cdc55133eb3162f8c1501ff3 Author: José Roberto de Souza <[email protected]> Date: Tue Jun 19 16:45:21 2018 -0700 intel: Introducing Amber Lake platform Amber Lake uses the same gen graphics as Kaby Lake, including a id that were previously marked as reserved on Kaby Lake, but that now is moved to AML page. So, let's just move it to AML macro that will feed into KBL macro just to keep it better organized to make easier future code review but it will be handled as a KBL. This is a copy of merged i915's commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform") Cc: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 44e65f9e..583d6447 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -201,7 +201,6 @@ #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915 #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E -#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912 #define PCI_CHIP_KABYLAKE_M_GT2 0x5917 #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902 @@ -213,6 +212,9 @@ #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0 + #define PCI_CHIP_BROXTON_0 0x0A84 #define PCI_CHIP_BROXTON_1 0x1A84 #define PCI_CHIP_BROXTON_2 0x5A84 @@ -468,12 +470,13 @@ #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \ (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \ - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \ (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \ (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \ - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2) + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \ + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \ + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2) #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \ (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \ commit 591c1d72abbc1ae67890a50dc107a0e4b9ef13c3 Author: José Roberto de Souza <[email protected]> Date: Tue Jun 19 16:45:20 2018 -0700 intel: Introducing Whiskey Lake platform Whiskey Lake uses the same gen graphics as Coffe Lake, including some ids that were previously marked as reserved on Coffe Lake, but that now are moved to WHL page. So, let's just move them to WHL macros that will feed into CFL macro just to keep it better organized to make easier future code review but it will be handled as a CFL. This is a copy of merged i915's commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform") Cc: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h index 32b2c48f..44e65f9e 100644 --- a/intel/intel_chipset.h +++ b/intel/intel_chipset.h @@ -231,16 +231,17 @@ #define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94 -#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1 -#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4 -#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0 -#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3 -#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9 -#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2 -#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5 -#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6 -#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7 -#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8 +#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9 +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5 +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6 +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7 +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8 + +#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1 +#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0 +#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2 +#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3 +#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4 #define PCI_CHIP_CANNONLAKE_0 0x5A51 #define PCI_CHIP_CANNONLAKE_1 0x5A59 @@ -510,16 +511,16 @@ #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2) -#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \ +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \ (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \ - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5) + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \ + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \ + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \ + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \ + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3) #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \ IS_CFL_H(devid) || \ ------------------------------------------------------------------------------ Check out the vibrant tech community on one of the world's most engaging tech sites, Slashdot.org! http://sdm.link/slashdot -- _______________________________________________ Dri-patches mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-patches