Re: 3D texture size limitations in mesa/r200?
Roland Scheidegger <[email protected]> Tue, 08 Jan 2008 20:27:54 +0100
| Newsgroups | gmane.comp.video.dri.user |
|---|---|
| Message-ID | <[email protected]> |
R. Aditya Kadambi wrote: > Alternatively, you could try out the attached quick patch against radeon > drm, which is completely untested. I guess the problem could be > fixed in > userspace instead by breaking up a single texture upload into several > smaller ones (ugly). > > Roland > > > Hi Roland; > > I just applied the patch. > > Well, even the smaller volumes (like 64x64x64 that used to work) don't > work with this patch. Sorry. Yes, there are obvious bugs in this patch. This one might work better. I think though it might be very broken (due to texture tiling) if texture width * texture bpp is not a multiple of 1024. Roland ------------------------------------------------------------------------- Check out the new SourceForge.net Marketplace. It's the best place to buy or sell services for just about anything Open Source. http://ad.doubleclick.net/clk;164216239;13503038;w?http://sf.net/marketplace -- _______________________________________________ Dri-users mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/dri-users
radeon_drm_large3dtex.diff
(text/x-patch, 1.2 KB)
diff --git a/shared-core/radeon_state.c b/shared-core/radeon_state.c
index 4c85371..03c8120 100644
--- a/shared-core/radeon_state.c
+++ b/shared-core/radeon_state.c
@@ -1663,7 +1663,7 @@ static int radeon_cp_dispatch_texture(st
u32 height;
int i;
u32 texpitch, microtile;
- u32 offset;
+ u32 offset, byte_offset;
RING_LOCALS;
if (radeon_check_and_fixup_offset(dev_priv, file_priv, &tex->offset)) {
@@ -1841,6 +1841,7 @@ static int radeon_cp_dispatch_texture(st
}
#undef RADEON_COPY_MT
+ byte_offset = (image->y / 2048) * image->width * (tex_width / tex->width);
buf->file_priv = file_priv;
buf->used = size;
offset = dev_priv->gart_buffers_offset + buf->offset;
@@ -1855,9 +1856,9 @@ static int radeon_cp_dispatch_texture(st
RADEON_DP_SRC_SOURCE_MEMORY |
RADEON_GMC_CLR_CMP_CNTL_DIS | RADEON_GMC_WR_MSK_DIS);
OUT_RING((spitch << 22) | (offset >> 10));
- OUT_RING((texpitch << 22) | (tex->offset >> 10));
+ OUT_RING((texpitch << 22) | ((tex->offset >> 10) + (byte_offset >> 10)));
OUT_RING(0);
- OUT_RING((image->x << 16) | image->y);
+ OUT_RING(((image->x + (byte_offset % 1024) / (tex_width / tex->width)) << 16) | (image->y % 2048));
OUT_RING((image->width << 16) | height);
RADEON_WAIT_UNTIL_2D_IDLE();
ADVANCE_RING();