Re: Regarding the memory alignment

After looking at the code, I've googled around and
found some interesting topics that may help.

http://softwarecommunity.intel.com/articles/eng/3011.htm

And here goes the fixed (it is broken there) link
suggested in that page:
http://softwarecommunity.intel.com/articles/eng/2990.htm

And this paper:
(specially page 30)
http://cache-www.intel.com/cd/00/00/09/28/92869_92869.pdf

XviD hasn't multi-threading support yet (AFAIK) but it
is planned. I guess aligning to the cache line is part
of the attempt to optimize it for multi-threading.
Besides 64 bytes is an interesting number, since most
L1 data caches are 64kb in size.

I'm afraid I can't help much more than this

Cheers
Dark Sylinc


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