Re: patch - word/byte PCI config support for ix86

On Sun, 9 Apr 2006, Sergey Babkin wrote:

> I'm not sure if it's a good idea to cc: to both X.org and
> XF86 mailing lists, but the subject is kind of useful
> for both.

> I've attached the patch that adds word- and byte-sized
> PCI configuration reads and writes for the ix86
> platform. The particular reason was to fix the
> support of sincgle-chip Matrox G200 with the VESA driver
> on UnixWare. This hardware is somewhat brain-damaged
> and really expects word- and byte-sized bus cycles,
> it does not work with the wraping in Long.

> I've added this support only to the type 1 configuration
> mode, since apparently type 2 hasn't been used in
> new devices for a few years now. The type 2 should
> still work in the old-fashioned way, by wrapping
> around through the Long read/write.

> It uses the fact that the register 0xCF8 gets written in
> a Long mode first to selec the bus address. During that
> write the hardware type detection will be triggered,
> and if the device uese type 1 configuration, then
> the pointers to the byte/word access functions would
> get populated, otherwise for type 2 they would be set to 0
> as before.

> Tha patch was done against the X.org 6.9.0 code.

This patch is incomplete.  There are no ...

- corresponding changes to Pci.h;
- checks for alignment;
- calls to these new functions;
- corresponding functions for other platforms.

Marc.

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