Re: siliconmotion CSync output ?
bruno schwander <[email protected]>
| Newsgroups | gmane.comp.xfree86.devel |
|---|---|
| Message-ID | <[email protected]> |
I used your vclk setting code as in smi_driver.c, and changed the shift in SMI_CommonCalcClock() but it seems to still have some issue. 12220 clock gives me values of SR6C: 63, SR6D: 1D bruno On Sun, 11 Mar 2007, Alex Deucher wrote: > On 3/10/07, bruno schwander <[email protected]> wrote: >> I looked at that diff and it looks like what I added, except that I also >> set bits 7:6 of CCR68 to 01 because the doc I have says that will select >> VCLK from the programmable VCLK regs, CCR6C and CCR6D. >> > > I fixed the vclk problem. The postscalar shift was wrong in > SMI_CalcClocks(). either grab my updated tree or change the shift > from 6 to 7. > > Alex > _______________________________________________ > Devel mailing list > [email protected] > http://XFree86.Org/mailman/listinfo/devel > >