Re: siliconmotion CSync output ?

On Mon, 12 Mar 2007, Alex Deucher wrote:

> On 3/12/07, bruno schwander <[email protected]> wrote:
>> I used your vclk setting code as in smi_driver.c, and changed the shift
>> in SMI_CommonCalcClock() but it seems to still have some
>> issue.
>> 
>> 12220 clock gives me values of
>> 
>> SR6C: 63, SR6D: 1D
>> 
>
> That's going to give you a vclk of ~48.88 Mhz

yeah, I know.

I meant that SMI_CommonCalcClock should have come up with different 
values, instead it returned the values above.

> Unfortunately, the min clock on the smi is 20 Mhz (although I'd think

hmm that would be really annoying...where do you get that ? I can't find 
any mention of such a limitation. Just the hope that given the right 
SR6C/D values, I can get any corresponding dot clock :-)

I did chnge the minclock values so that it accepts lower clock requests, 
but I have not checked it it actually generates those frequencies. Need 
the scope...

> you should be able to get down to at least the reference clock), so
> that may be causing a problem in the calculation function.  If you
> want to calculate the clock yourself you can use the following
> formula:
>
> VCLK = 14.31818 Mhz * (VNR/VDR) * (1/(1 + PS))
>
> VNR being SR6C and VDR and SR6D.  PS is bit 7 of SR6D.

the spec I have for the smi712 (lynxEM+) says bit 7 and 6 are PS, 
as follows:

bit 6  bit 7      vclk
0      0          PS not enabled, programmed vclk
0      1          PS enabled, vclk = 1/2 programmed vclk
1      0          PS enabled, vclk = 1/4 prog vlck
1      1          PS enabled, vclk = 1/8 prog vlck


bruno