regular expression problem

Hi,

I have created a small macro to help me to modify some Verilog files to
replace a line that contains some characters followed or not by a comma
by the same line starting with 'input' and ending by a comma.
Ex :
the line contains :
toto
or the line contains :
toto,

In both case, I want to replace it by :
input toto,

The result I get is :
if the line does not contain any comma, then it works.
If the line already contains a comma, the resulting line contains 2 commas.

Could you help me ?

Regards.

Eric.
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