CVS update by mharnisch packages/xemacs-packages/prog-modes ...

  User: mharnisch
  Date: 09/01/06 21:53:35

  Modified:    packages/xemacs-packages/prog-modes prog-modes.texi
Log:
Update section about verilog-mode.

Revision  Changes    Path
1.7       +18 -9     XEmacs/packages/xemacs-packages/prog-modes/prog-modes.texi

Index: prog-modes.texi
===================================================================
RCS file: /pack/xemacscvs/XEmacs/packages/xemacs-packages/prog-modes/prog-modes.texi,v
retrieving revision 1.6
retrieving revision 1.7
diff -u -p -r1.6 -r1.7
--- prog-modes.texi	2004/08/15 17:38:03	1.6
+++ prog-modes.texi	2009/01/06 20:53:34	1.7
@@ -1948,11 +1948,11 @@ The Motif user interface language (UIL) 
 describing the initial state of a Motif application's user interface.
 
 @node verilog-mode, vrml-mode, uil-mode, Top
-@chapter Editing Verilog HDL Source
+@chapter Editing Verilog and SystemVerilog HDL Source
 
-This mode is used to edit Verilog source files.  It is automatically invoked
-for buffers visiting any file ending with one of the following extensions:
-@file{.vh?}, @file{.dv}, @file{.vlog}, and @file{.verilog}.
+This mode is used to edit Verilog and SystemVerilog source files.  It
+is automatically invoked for buffers visiting any file ending with one
+of the following extensions: @file{.vh?}, @file{.svh?}, @file{.dv}.
 
 The mode provides the following features:
 
@@ -1960,8 +1960,14 @@ The mode provides the following features
 @item NEWLINE, TAB indents for Verilog code.
 @item Delete converts tabs to spaces as it moves back.
 @item Supports highlighting.
+@item Supports SystemVerilog OVM (Open Verification Methodology) macros.
 @end itemize
 
+This documentation is only a teaser and does not claim to be
+complete. Please check out
+@uref{http://www.veripool.org/wiki/verilog-mode/Documentation}
+for further information, FAQ and change history.
+
 The variables controlling indentation/edit style are:
 
 @table @code
@@ -2169,13 +2175,16 @@ To configure this package, type:
 
 @node about-verilog,  , verilog-mode, verilog-mode
 @section About Verilog
+
+Verilog (IEEE 1364) and SystemVerilog (IEEE 1800) HDL are hardware
+description languages used to design and document electronic
+systems. In December 2007 IEEE 1364 has been merged into IEEE 1800,
+paving the way for SystemVerilog as the official successor to Verilog.
 
-Verilog HDL is a hardware description language used to design and document
-electronic systems. Verilog HDL allows designers to design at various levels
-of abstraction. It is the most widely used HDL with a user community of more
-than 50,000 active designers.
+SystemVerilog HDL allows designers to design at various levels of
+abstraction.
 
-For more information, see @uref{http://www.verilog.com/}.
+For more information, see @uref{http://www.systemverilog.org/}.
 
 @node vrml-mode, XEmacs License, verilog-mode, Top
 @chapter Editing VRML (.wrl) Files