Re: [PATCH RFC 1/7] ACPICA: Define PCIe P2P latency and bandwidth information

On Thu, Aug 13, 2026 at 12:13:39PM +0200, Rafael J. Wysocki (Intel) wrote:
> On Wed, Aug 12, 2026 at 9:48 PM Leon Romanovsky <[email protected]> wrote:
> >
> > From: Leon Romanovsky <[email protected]>
> >
> > PCIe topology alone cannot tell an operating system whether traffic may
> > cross host bridges, what ordering rules it needs, or how expensive the path
> > is. Encoding this knowledge in chipset lists duplicates platform policy and
> > cannot survive a virtualized topology.
> >
> > Define HMAT Type 3 as a firmware contract for directional Generic Port P2P
> > paths, including separate ordered and Unordered I/O applicability. This
> > gives platform software a standard way to distinguish unsupported,
> > conditional, and usable paths. The definition follows a proposed ACPI ECN.
> >
> > Signed-off-by: Leon Romanovsky <[email protected]>
> > ---
> >  include/acpi/actbl1.h | 27 ++++++++++++++++++++++++++-
> >  1 file changed, 26 insertions(+), 1 deletion(-)
> 
> As per Documentation/driver-api/acpi/linuxized-acpica.rst, please
> submit a pull request with this change to the upstream ACPICA project
> on GitHub.  The Linux patch will become applicable when there is a
> corresponding commit upstream.

Sure, we will. However, at this stage, we are looking for
feedback on the idea.

Thanks.