[coreboot - Bug #512] 1MiB heap breaks TSEG stage cache resume on many platforms
Andrei Purdea <[email protected]>
| Newsgroups | gmane.linux.bios |
|---|---|
| Message-ID | <[email protected]> |
Issue #512 has been updated by Andrei Purdea.
A number of libreboot users are also experiencing this, see here: https://codeberg.org/libreboot/lbmk/issues/140
Either disabling Stage Cache, or increasing SMM_RESERVED_SIZE makes the problem go away.
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Bug #512: 1MiB heap breaks TSEG stage cache resume on many platforms
https://ticket.coreboot.org/issues/512#change-1687
* Author: Bill XIE
* Status: Needs Testing
* Priority: High
* Assignee: Patrick Georgi
* Category: coreboot common code
* Target version: master
* Start date: 2023-10-27
* Affected versions: master
* Related links: https://review.coreboot.org/c/coreboot/+/78270
https://review.coreboot.org/c/coreboot/+/78623
* Affected hardware: GM45, Ivy Bridge
* Affected OS: GNU/Linux
----------------------------------------
commit 44a48ce7a46c ("Kconfig: Bring HEAP_SIZE to a common, large value") proves to break S3 resume from TSEG stage cache on many platforms, including GM45 and Ivy Bridge.
```
coreboot-4.21-587-g9b230ae29557 Fri Oct 13 18:35:11 UTC 2023 x86_32 postcar starting (log level: 7)...
Timestamp - start of postcar: 248582576
Timestamp - end of postcar: 248589814
S3 Resume
Error: Can't find stage_cache 57a9e100 in imd
ramstage cache invalid.
board_reset() called!
system_reset() called!
```
It seems that the commit above has not experienced many test for S3 resume before getting merged.
The default heap size may have to be reconsidered.
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