RFCv3: Post-build control of serial console

Hi,

I sent an updated CL for this here:

https://review.coreboot.org/c/coreboot/+/77712

There are a few questions to resolve. As an example, here is the bootblock
output on brya that can be controlled with this RFC.

[NOTE ]  coreboot-coreboot-unknown.9999.915d387 Wed Nov 15 17:48:38 UTC
2023 x86_32 bootblock starting (log level: 8)...
[DEBUG]  CPU: 12th Gen Intel(R) Core(TM) i3-1215U[DEBUG]  CPU: ID 906a4,
Alderlake R0 Platform, ucode: 00000430
[DEBUG]  CPU: AES supported, TXT NOT supported, VT supported[INFO ]  Cache:
Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384
[INFO ]  Cache size = 10 MiB[DEBUG]  MCH: device id 4609 (rev 04) is
Alderlake-P
[DEBUG]  PCH: device id 5182 (rev 01) is Alderlake-P SKU[DEBUG]  IGD:
device id 46b3 (rev 0c) is Alderlake P GT2
[INFO ]  VBNV: CMOS invalid, restoring from flash[DEBUG]  FMAP: Found
"FLASH" version 1.1 at 0x1804000.
[DEBUG]  FMAP: base = 0x0 size = 0x2000000 #areas = 35[DEBUG]  FMAP: area
RW_NVRAM found @ f2b000 (24576 bytes)
[INFO ]  SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
[INFO ]  VBNV: Restore from flash failed
[INFO ]  Probing TPM I2C: I2C bus 1 version 0x3230302a
[INFO ]  DW I2C bus 1 at 0xfe022000 (400 KHz)
[ERROR]  I2C TX abort detected (00000001)
[ERROR]  cr50_i2c_read: Address write failed
[INFO ]  .done! DID_VID 0x00281ae0
[INFO ]  TPM ready after 0 ms
[DEBUG]  cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
[INFO ]  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de
RW_A:0.6.201/cr50_v3.9
[ERROR]  Current CR50_BOARD_CFG = 0x80000001, does not matchdesired =
0x00000000
[INFO ]  tlcl_send_startup: Startup return code is 0x0
[INFO ]  TPM: setup succeeded
[INFO ]  src/security/tpm/tss/tcg-2.0/tss.c:253 index 0x1007 return code 0x0
[INFO ]  src/security/tpm/tss/tcg-2.0/tss.c:253 index 0x1008 return code 0x0
[DEBUG]  Chrome EC: UHEPI supported
[DEBUG]  Reading cr50 boot mode
[INFO ]  GSC says boot_mode is VERIFIED_RW(0x00).
[INFO ]  Phase 1
[DEBUG]  FMAP: area GBB found @ 1805000 (458752 bytes)
[INFO ]  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 /
0x0
[INFO ]  Phase 2
[INFO ]  Phase 3
[DEBUG]  FMAP: area GBB found @ 1805000 (458752 bytes)
[DEBUG]  FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
[DEBUG]  FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
[INFO ]  VB2:vb2_verify_keyblock() Checking keyblock signature...
[INFO ]  VB2:vb2_digest_init() 1144 bytes, hash algo 3, HW acceleration
unsupported
[INFO ]  VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using
SW
[INFO ]  VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported,
using SW
[DEBUG]  FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
[DEBUG]  FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
[INFO ]  VB2:vb2_verify_fw_preamble() Verifying preamble.
[INFO ]  VB2:vb2_digest_init() 1652 bytes, hash algo 2, HW acceleration
enabled
[INFO ]  VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using
SW
[INFO ]  VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported,
using SW
[INFO ]  Phase 4
[DEBUG]  FMAP: area FW_MAIN_A found @ 510000 (8323008 bytes)
[INFO ]  VB2:vb2_digest_init() 4353856 bytes, hash algo 2, HW acceleration
enabled
[INFO ]  VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using
SW
[INFO ]  VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported,
using SW
[DEBUG]  Saving vboot hash.
[INFO ]  Saving nvdata
[DEBUG]  TPM: Extending digest for `VBOOT: boot mode` into PCR 0
[INFO ]  tlcl_extend: response is 0x0
[DEBUG]  TPM: Digest of `VBOOT: boot mode` to PCR 0 measured
[DEBUG]  TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1
[INFO ]  tlcl_extend: response is 0x0
[DEBUG]  TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured
[INFO ]  tlcl_lock_nv_write: response is 0x0
[INFO ]  tlcl_lock_nv_write: response is 0x0
[INFO ]  Slot A is selected
[DEBUG]  FMAP: area FW_MAIN_A found @ 510000 (8323008 bytes)
[INFO ]  CBFS: mcache @0xfef89600 built for 23 files, used 0x47c of 0x2000
bytes

(at this point CBFS is active)

[DEBUG]  FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
[INFO ]  CBFS: mcache @0xfef87600 built for 67 files, used 0xe84 of 0x2000
bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x0 size 0x1ff90 in mcache
@0xfef89600
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 445 ms

Regards,
Simon

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