Technical details of VGA text mode in coreboot romstage

Hi  Jérémy,

In the original thread about romstage VGA text mode on the coreboot 
mailing list [1], some ideas were brought up about using this 
functionality for early debug messages and porting this to older 
platforms. I was interested in these possibilities and started exploring 
an implementation for Ivy Bridge, so I was wondering if you know and are 
able to share more information about how this works on Alder Lake and if 
this is even theoretically possible on older platforms.

 From what I understand, accesses to the legacy VGA range from 0xA0000 
to 0xBFFFF are forwarded to integrated graphics, assuming various config 
registers are set up appropriately. The Programmer's Reference Manuals 
state that the iGPU uses the preallocated graphics stolen memory range 
under TOLUD to support VGA graphics: "VGA graphics memory starts from 
the base of graphics data stolen memory defined in the PCI configuration 
BDSM register. VGA display uses the first four 64KB pages of VGA 
graphics memory" [2, pp. 22].

In the case of romstage graphics, there isn't DRAM to back the stolen 
memory range, so where exactly is this data being stored? My best 
guesses are the shared last level cache, the internal iGPU caches, or 
perhaps some other internal buffer. From the initial implementation of 
romstage graphics [3], there doesn't seem to be any other initialization 
being done other than setting up the iGPU GTTMMADR BAR for MMIO access, 
turning on the panel backlight, running libgfxinit, and running VGA init.

I had attempted to replicate these initialization steps on Ivy Bridge 
and found that the earliest point that I could run romstage graphics 
without the boot process freezing on clearing the VGA framebuffer was 
just after normal DRAM operation was enabled in raminit, which suggests 
to me that the accesses were going out to the main memory which was not 
yet functioning if graphics was enabled beforehand.

Does Alder Lake behave differently such that this "just works" out of 
the box without any additional initialization steps, or is there some 
additional initialization happening elsewhere to set up some sort of 
backing store?

Cheers,
Nicholas

[1] 
https://mail.coreboot.org/hyperkitty/list/[email protected]/thread/2DYBF6OAUT4N4HHQVP6ZCCFDVC757TD6/#VJRIDL2V763EA7D4E5SI2VLFGSYSYAVB

[2] 
https://cdrdv2-public.intel.com/705833/intel-gfx-prm-osrc-tgl-vol-12-display-engine.pdf

[3] 
https://review.coreboot.org/q/topic:%22romstage-early-graphics-for-memory-training%22

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