Question about DISB handling in memory init

Hello there,

I have been studying the memory initialization process on the Alder
Lake platform, like what's going on before and after utilizing FSP-M
binary.

And while I was studying sources I stumbled upon the following function
(src/soc/intel/alderlake/pmutil.c):

```
/* Set the DISB after DRAM init */
void pmc_set_disb(void);
```

It's actually defined in every Intel SoC header and contains
SoC-specific implementation. The comment and name function assert that
func sets the DISB bit. And yes, it does it.

However, I opened Intel 600 Series Chipset Family for IoT Edge Platform
Controller Hub (PCH) Datasheet, Volume 2 (dated October 2022, Revision
001) and it asserts the opposite:

```
DRAM Initialization Scratchpad Bit (DISB):
<skipped text>. BIOS is expected to set this bit prior to starting the
DRAM initialization sequence and to clear this bit after completing the
DRAM initialization sequence. BIOS can detect that a DRAM
initialization sequence was interrupted by a reset by reading this bit
during the boot sequence. If the bit is 1, then the DRAM initialization
was interrupted.
```

So it suggests *clearing* the bit after DRAM init. Why does coreboot do
the opposite? I was trying to study git history to find out, but it
didn't give me any answer to my question as well.

So maybe somebody on the mailing list knows more about it? Is it a typo
in the Intel docs?

-- 
Joursoir
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