Re: Two devicetree questions and two use cases
Nicholas Chin <[email protected]>
| Newsgroups | gmane.linux.bios |
|---|---|
| Message-ID | <[email protected]> |
Hi Keith, I can't speak to the devicetree stuff, but I did find something interesting regarding the PCH PCIe ports: > p8z77-v and sabertooth_z77 have a third PCIe x4 slot serviced by the > PCH, but the 4 lanes are shared with some other x1 slots and devices. > They can configure the PCIe x4 slot to really be x4, or the 4 lanes > can be configured as 4 x1 ports for various x1 slots or onboard > devices. This requires changing a soft strap as well as manipulating > some GPIOs in the SIO chip, and the devicetree changed to match. I > have the SIO GPIO part figured out, the soft strap I can only come to > one possible explanation: reflash SPI descriptor with the changed soft > strap and force a platform reset. To verify I'll need to get a board > and actually check the flash chip for changes. Changing the IFD at runtime seems like an impractical way to achieve this, especially since the IFD is normally supposed to be read only. I suspect there's another, undocumented method to change the configuration. On ICH/PCH datasheets, there is an RCBA register (Root Port Configuration Register) that indicates the current port configuration. On the 7 series PCH's, that is at RCBA32(0x400), bits 3:2 for ports 5-8 and bits 1:0 for ports 1:4. However, these bitfields are documented as read only in the public datasheets. However, in the public ICH9 datasheet (and seemingly only the ICH9 datasheet; other datasheets like ICH7, ICH8, ICH10, etc don't have this detail) the equivalent register at RCBA32(0x224) lists the bitfields as R/W, with a note saying that writing to them is for debug/testing and should be treated as read only and modifiable only through hard straps (it seems like ICH9 didn't use IFD soft straps for this). Based on that note, I assume this mechanism is intended for testing different PCH PCIe configurations without reflashing the IFD. I haven't tested this yet on any platform but it does seem plausible that this mechanism exists on chipsets other than ICH9. Cheers, Nicholas _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected]