Re: Two devicetree questions and two use cases

On 2025-01-16 00:48, Keith Hui wrote:
> The board is here. For some reason both my old Fedora installation and 
> SystemRescue failed to boot on it so I can't run autoport yet.
> 
> However, I did change that PCIe bandwidth setting and took a SPI flash 
> dump before and after. That PCH soft strap DID change.
> 
> Where do we go from here?
> 
> Thanks
> Keith

Hmm, interesting. There are some boards that don't seem to have a UEFI 
option to change the bandwidth, and instead change it depending on 
whether a slot is populated or not. From what I understand doing that 
with the IFD would require booting, detecting a card being present, 
reflashing the IFD, and rebooting; all without any indication to the 
user. So hypothetically, just plugging in a PCIe card could soft brick 
the system if something went wrong while reflashing the IFD. At least 
with the UEFI setting a user has to intentionally make a change before 
the IFD is reflashed.

I know someone with a Haswell board that does it at runtime; I'll see if 
we can experiment and determine if it's actually reflashing the IFD at 
runtime or if it seems to be doing something else. That said, UEFItool 
does show a DXE called "DescriptorUpdate", which might suggest that it 
is indeed rewriting the descriptor. But it's hard to say without digging 
further into the firmware what that is actually used for. I'd hope that 
the behavior on Haswell chipsets is similar to Ivy Bridge chipsets, 
though I did notice that the Root Port Configuration Register on Haswell 
would always return 0, whereas on Ivy Bridge the same register would 
contain values that reflected what was set in the IFD.

 From experimentation, it seems like the RPC register is indeed writable 
on ICH9 like the datasheet suggests, and that results in the PCI config 
registers for the root ports reporting different widths for the link 
capabilities depending on the value written to the RPC register. I don't 
have any way to test if the ports actually operate as wider widths 
though since all of those are routed to mPCIe slots or the Expresscard, 
which are all x1 links. Interestingly it also doesn't seem to hide the 
PCI device for the root ports that shouldn't be available due to their 
lanes being assigned to a different root port operating with a wider 
link width, and thus it appears that there are more total PCIe lanes 
than are physically present. As I've mentioned before, writing to that 
register on Ivy Bridge and Haswell seems to have no effect.

I guess this doesn't really get us anywhere other than suggesting that 
the PCH soft straps are indeed the only way to change things on newer 
chipsets.

Cheers,
Nicholas
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