ARL-HX: Separate SoC and PCH contexts

We have hit some blockers with porting Clevo ARL-HX boards that I'm hoping to get feedback about how to address.

1. PCIe devices for SoC and PCH are declared on separate buses.

- SoC: Devices on bus 0x00
- PCH: Devices on bus 0x80

There are conflicts between device/function that would prevent us from declaring them on the same bus. For example,

    $ lspci -Dtvnn -s 14.0
    -+-[0000:00]---14.0  Intel Corporation Device [8086:ae7f] <-- Shared SRAM (SOC-S)
     \-[0000:80]---14.0  Intel Corporation Device [8086:7f6e] <-- USB 3.1 xHCI HC

We'd like to match this layout when porting new boards, but I don't think devicetree supports specifying the bus. And I don't know what else would need to change to handle it.

2. GPIO access for SoC and PCH are separate. 

I have a lot less understanding about what's happening here and what's required.

One detail I got from Jeremy while he was trying to port a board was that this would impact ACPI/acpigen code:

> the GPIOs in the first PCR region are from the CPU, and the PCH GPIOs are in another PCR region. I need to set the GPIOs for the PCH but none of the current coreboot code would work without specifying which PCR region to address.

Looking at the ACPI dump of a board, I see SoC and PCH devices are in separate regions.

- SoC: Uses `\_SB.PC00`
- PCH: Uses `\_SB.PC02`

-- 
Tim Crawford
System76
Kernel Engineer
[email protected]
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