Re: Does coreboot support "Extended Address Register" to use >16MB chips in 3BA mode?

Hi Mike,

The access via the SPI controller registers isn't a legacy method; even 
on the current SoCs coreboot uses that for writes to the SPI flash. This 
interface can be used to send raw commands to the SPI flash; at least 
unless the SPI controller is locked down in some way. The code for using 
the SPI controller in upstream coreboot is for the newer SPI100 SPI 
controller; don't remember when the pre-Zen SoCs switched form the older 
SPI controller to the SPI100 controller, so might be that the chip 
you're interested in uses the older SPI controller. Haven't checked, but 
I'd expect that the code for the old chips will have support for the 
corresponding SPI controller.
Using that interface you could possibly even use 4 byte addressing mode, 
but it's slower than MMIO and needs a special driver instead of just 
mmap-ing the data. Trying to use the 3 byte address with extended 
address register mode (which is basically a bank-switching mode) 
probably won't end up too well, since when changing the value in the 
extended address register, the MMIO accesses which are internally 
translated to 3 byte address SPI read commands will read from the wrong 
part of the SPI flash. When trying that, make sure that you put coreboot 
in the correct 16MBytes of the flash. You'd need to check the SPI flash 
datasheet which one that is, but I'd expect that by default you'll 
access the first 16MBytes using the 3 byte addressing.

Regards,
Felix
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