Native RAM Init: Logs of *Haswell NRI: Implement 1D margin training*
Paul Menzel <[email protected]> Sat, 21 Feb 2026 19:52:26 +0100
| Newsgroups | gmane.linux.bios |
|---|---|
| Message-ID | <[email protected]> |
Dear coreboot community,
Angel uploaded patchset 5 of their change-set/commit *Haswell NRI:
Implement 1D margin training* [1], and shared the debug logs [2]. Great
work and interesting to me.
Kind regards,
Paul
[1]: https://review.coreboot.org/c/coreboot/+/89314
[2]: https://paste.flashrom.org/view.php?id=3808
PS: Excerpt:
```
Bit lane information
Channel 0
Byte 0 1 2 3 4 5 6 7
Bit 0123456701234567012345670123456701234567012345670123456701234567
WrDqsDelay
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16 ####################.#######.####.#########################.###.
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Channel 1
Byte 0 1 2 3 4 5 6 7
Bit 0123456701234567012345670123456701234567012345670123456701234567
WrDqsDelay
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C0.R0: Left Right Width Center
B0: -31 11 42 -10
B1: -31 10 41 -11
B2: -31 12 43 -10
B3: -31 13 44 -9
B4: -31 12 43 -10
B5: -31 10 41 -11
B6: -31 10 41 -11
B7: -31 13 44 -9
C1.R0: Left Right Width Center
B0: -25 19 44 -3
B1: -23 14 37 -5
B2: -25 16 41 -5
B3: -26 20 46 -3
B4: -25 16 41 -5
B5: -24 13 37 -6
B6: -23 17 40 -3
B7: -23 14 37 -5
```
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