Re: Request for Guidance on Coreboot Porting for Raptor Lake-S RVP + DDR5 Motherboard
"Keshavamurthy K [Firmware-NTL] via coreboot" <[email protected]> Wed, 17 Jun 2026 11:35:50 +0000
| Newsgroups | gmane.linux.bios |
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| Message-ID | <PN2P287MB0416BB21C6D93E237DC4D0AB8EE42@PN2P287MB0416.INDP287.PROD.OUTLOOK.COM> |
--===============8837825314143905452== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_PN2P287MB0416BB21C6D93E237DC4D0AB8EE42PN2P287MB0416INDP_" --_000_PN2P287MB0416BB21C6D93E237DC4D0AB8EE42PN2P287MB0416INDP_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hello All, Thank you for the guidance and warnings regarding cross-flashing. Based on = your recommendations, I will avoid flashing an ADL_RVP image directly onto = another board and will proceed with creating a dedicated board port first. I have another question regarding the ADL_RVP build. I am able to successfu= lly generate a ROM image using the existing ADL_RVP configuration. However,= when I try to enable and add a bootsplash image through make menuconfig, t= he build process stops with an error. Are there any known limitations, depe= ndencies, or configuration requirements for bootsplash support on Alder Lak= e RVP platforms? I would also appreciate some guidance on GPIO configuration for a new board= port. My understanding is that GPIOs must be adapted carefully before any = hardware testing. Is the recommended workflow still: 1. Boot the vendor firmware. 2. Use util/inteltool to dump GPIO/pad configuration. 3. Use util/intelp2m to generate the initial GPIO definitions. 4. Create the board-specific GPIO configuration and reference it from th= e mainboard .cb files. Are there any examples of recent Alder Lake or Raptor Lake mainboards that = demonstrate the preferred way of defining GPIO configuration in the device = tree (.cb) and corresponding gpio.c/gpio.h files? Thank you again for your support and recommendations. Best Regards, Keshavamurthy K ________________________________ From: Alicja Michalska <[email protected]> Sent: Tuesday, June 16, 2026 6:30 PM To: [email protected] <[email protected]> Subject: [coreboot] Re: Request for Guidance on Coreboot Porting for Raptor= Lake-S RVP + DDR5 Motherboard [You don't often get email from [email protected]. Learn why this is impor= tant at https://aka.ms/LearnAboutSenderIdentification ] Ditto, please *never* cross-flash "similar" boards. I've had people who wer= e new to firmware development come up to me during conferences say they fri= ed their boards by doing so (and had no idea why). On 16/06/2026 14:48, Florian Jung via coreboot wrote: > Hi Keshavamurthy, > > Am 16.06.26 um 14:12 schrieb Keshavamurthy K [Firmware-NTL] via coreboot: >> Would it be safe and appropriate to flash a Coreboot ROM generated from = the ADL_RVP configuration directly onto the Intel ADL RVP DDR5 board for ea= rly testing, or would you recommend first creating a dedicated mainboard po= rt and adapting the GPIO, memory, PCIe, and board-specific configuration be= fore attempting any flashing? > > You absolutely need to adapt GPIO configuration. Not doing so may cause p= ermanent hardware damage, if GPIOs are mismatched in a way that your firmwa= re drives a GPIO pin while it's externally driven, too. > > There should not be any dangerous issues because of memory or PCIe-relate= d configuration, but you can also not expect that it'll just work. > > I'd do the porting beforehand, you'll need to do it anyway. > > Best, > Florian > > _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] Note : " We Never inform change of Bank details by email. If you receive an= y such emails from our domain/users. Please don't respond, and contact us s= eparately " --_000_PN2P287MB0416BB21C6D93E237DC4D0AB8EE42PN2P287MB0416INDP_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <html> <head> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3Diso-8859-= 1"> <style type=3D"text/css" style=3D"display:none;"> P {margin-top:0;margin-bo= ttom:0;} </style> </head> <body dir=3D"ltr"> <div class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;= font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, Calibri, Helv= etica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> Hello All,</div> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">Tha= nk you for the guidance and warnings regarding cross-flashing. Based on your recommendations, I will avoid flashing an AD= L_RVP image directly onto another board and will proceed with creating a de= dicated board port first.</span></p> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">I h= ave another question regarding the ADL_RVP build. I am able to successfully generate a ROM image using the existing A= DL_RVP configuration. However, when I try to enable and add a bootsplash im= age through <code>make menuconfig</code>, the build process stops with an error. Are th= ere any known limitations, dependencies, or configuration requirements for = bootsplash support on Alder Lake RVP platforms? </span></p> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">I w= ould also appreciate some guidance on GPIO configuration for a new board port. My understanding is that GPIOs mu= st be adapted carefully before any hardware testing. Is the recommended wor= kflow still:</span></p> <ol start=3D"1"> <li style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService, C= alibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <p class=3D"elementToProof" role=3D"presentation" style=3D"margin-top: 1em;= margin-bottom: 1em;"> Boot the vendor firmware.</p> </li><li style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontServi= ce, Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <p class=3D"elementToProof" role=3D"presentation" style=3D"margin-top: 1em;= margin-bottom: 1em;"> Use <code>util/inteltool</code> to dump GPIO/pad configuration.</p> </li><li style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontServi= ce, Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <p class=3D"elementToProof" role=3D"presentation" style=3D"margin-top: 1em;= margin-bottom: 1em;"> Use <code>util/intelp2m</code> to generate the initial GPIO definition= s.</p> </li><li style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontServi= ce, Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);"> <p class=3D"elementToProof" role=3D"presentation" style=3D"margin-top: 1em;= margin-bottom: 1em;"> Create the board-specific GPIO configuration and reference it from the main= board <code> .cb</code> files.</p> </li></ol> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">Are= there any examples of recent Alder Lake or Raptor Lake mainboards that demonstrate the preferred way of defining G= PIO configuration in the device tree (<code>.cb</code>) and corresponding <code>gpio.c</code>/<code>gpio.h</code> files?</span></p> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">Tha= nk you again for your support and recommendations.</span></p> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">Bes= t Regards,</span></p> <p class=3D"elementToProof" style=3D"margin-top: 1em; margin-bottom: 1em;">= <span style=3D"font-family: Aptos, Aptos_EmbeddedFont, Aptos_MSFontService,= Calibri, Helvetica, sans-serif; font-size: 12pt; color: rgb(0, 0, 0);">Kes= havamurthy K</span></p> <div><span style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; fon= t-size: 12pt; color: rgb(0, 0, 0);"><br> </span></div> <hr style=3D"display: inline-block; width: 98%;"> <div style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; font-size= : 12pt; color: rgb(0, 0, 0);"> <b>From:</b> Alicja Michalska <[email protected]><br> <b>Sent:</b> Tuesday, June 16, 2026 6:30 PM<br> <b>To:</b> [email protected] <[email protected]><br> <b>Subject:</b> [coreboot] Re: Request for Guidance on Coreboot Portin= g for Raptor Lake-S RVP + DDR5 Motherboard </div> <div style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; font-size= : 12pt; color: rgb(0, 0, 0);"> <br> </div> <div style=3D"font-size: 11pt;">[You don't often get email from ahplka19@gm= ail.com. Learn why this is important at <a href=3D"https://aka.ms/LearnAboutSenderIdentification" id=3D"OWA19a72cef= -6c0f-6ffa-89b8-a5177cda1f86" class=3D"OWAAutoLink" data-auth=3D"NotApplica= ble"> https://aka.ms/LearnAboutSenderIdentification</a> ]<br> <br> Ditto, please *never* cross-flash "similar" boards. I've had peop= le who were new to firmware development come up to me during conferences sa= y they fried their boards by doing so (and had no idea why).<br> <br> On 16/06/2026 14:48, Florian Jung via coreboot wrote:<br> > Hi Keshavamurthy,<br> ><br> > Am 16.06.26 um 14:12 schrieb Keshavamurthy K [Firmware-NTL] via corebo= ot:<br> >> Would it be safe and appropriate to flash a Coreboot ROM generated= from the ADL_RVP configuration directly onto the Intel ADL RVP DDR5 board = for early testing, or would you recommend first creating a dedicated mainbo= ard port and adapting the GPIO, memory, PCIe, and board-specific configuration before attempting any flashing?<br> ><br> > You absolutely need to adapt GPIO configuration. Not doing so may caus= e permanent hardware damage, if GPIOs are mismatched in a way that your fir= mware drives a GPIO pin while it's externally driven, too.<br> ><br> > There should not be any dangerous issues because of memory or PCIe-rel= ated configuration, but you can also not expect that it'll just work.<br> ><br> > I'd do the porting beforehand, you'll need to do it anyway.<br> ><br> > Best,<br> > Florian<br> ><br> ><br> _______________________________________________<br> coreboot mailing list -- [email protected]<br> To unsubscribe send an email to [email protected]<br> </div> Note : " We Never inform change of Bank details by email. If you recei= ve any such emails from our domain/users. Please don’t respond, and c= ontact us separately " </body> </html> --_000_PN2P287MB0416BB21C6D93E237DC4D0AB8EE42PN2P287MB0416INDP_-- --===============8837825314143905452== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] --===============8837825314143905452==--