porting coreboot to Enter ATX Motherboard E-G41D2

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Hi all,
I am planning to port coreboot to the *Enter ATX E-G41D2* (Intel G41 +
ICH7), a low-cost, popular alternative to the supported *Gigabyte
GA-G41M-ES2L* in the Indian market.

Using the gigabyte/ga-g41m-es2l port as a baseline, I have a few quick
questions before I begin:

   1.

   *GPIO Mapping:* Is dumping registers via inteltool the most reliable
   method to identify ICH7 GPIO differences from the vendor BIOS?
   2.

   *Super I/O Delta:* If the physical Super I/O chip differs from
   Gigabyte's ITE IT8718F, which primary configuration files (aside from
   Kconfig and devicetree.cb) require updates?
   3.

   *Native Raminit:* Are there any known routing or DIMM slot layout edge
   cases that cause native x4x raminit to fail on non-reference boards?

I will be backing up the stock ROM externally using a CH341A programmer
before flashing anything. Any advice or architectural pitfalls regarding
this chipset family would be greatly appreciated.

Best regards,
Ashok

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<div dir=3D"ltr">Hi all,<div><span style=3D"background-color:transparent">I=
 am planning to port coreboot to the </span><b style=3D"background-color:tr=
ansparent">Enter ATX E-G41D2</b><span style=3D"background-color:transparent=
"> (Intel G41 + ICH7), a low-cost, popular alternative to the supported </s=
pan><b style=3D"background-color:transparent">Gigabyte GA-G41M-ES2L</b><spa=
n style=3D"background-color:transparent"> in the Indian market.</span><p>Us=
ing the <code>gigabyte/ga-g41m-es2l</code> port as a baseline, I have a few=
 quick questions before I begin:</p><ol start=3D"1"><li><p><b>GPIO Mapping:=
</b> Is dumping registers via <code>inteltool</code> the most reliable meth=
od to identify ICH7 GPIO differences from the vendor BIOS?</p></li><li><p><=
b>Super I/O Delta:</b> If the physical Super I/O chip differs from Gigabyte=
&#39;s ITE IT8718F, which primary configuration files (aside from <code>Kco=
nfig</code> and <code>devicetree.cb</code>) require updates?</p></li><li><p=
><b>Native Raminit:</b> Are there any known routing or DIMM slot layout edg=
e cases that cause native <code>x4x</code> raminit to fail on non-reference=
 boards?</p></li></ol><p>I will be backing up the stock ROM externally usin=
g a CH341A programmer before flashing anything. Any advice or architectural=
 pitfalls regarding this chipset family would be greatly appreciated.</p><d=
iv><br></div><div>Best regards,</div><div>Ashok</div></div></div>

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