Re: porting coreboot to Enter ATX Motherboard E-G41D2
Heitor Ramos Assunção <[email protected]> Fri, 26 Jun 2026 13:06:58 +0000
| Newsgroups | gmane.linux.bios |
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| Message-ID | <EA2P220MB1818F562B16134188FA814939DEB2@EA2P220MB1818.NAMP220.PROD.OUTLOOK.COM> |
--===============6369601862610511392== Content-Language: pt-BR Content-Type: multipart/alternative; boundary="_000_EA2P220MB1818F562B16134188FA814939DEB2EA2P220MB1818NAMP_" --_000_EA2P220MB1818F562B16134188FA814939DEB2EA2P220MB1818NAMP_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable And pls commit the port in the review.coreboot.org Obter o Outlook para Android<https://aka.ms/AAb9ysg> ________________________________ From: Florian Jung via coreboot <[email protected]> Sent: Friday, 26 June 2026 08:36:56 To: [email protected] <[email protected]> Subject: [coreboot] Re: porting coreboot to Enter ATX Motherboard E-G41D2 Hi Ashok, Am 26.06.26 um 07:16 schrieb Ashok Arora: > Hi all, > I am planning to port coreboot to the *Enter ATX E-G41D2*(Intel G41 + > ICH7), a low-cost, popular alternative to the supported *Gigabyte GA- > G41M-ES2L*in the Indian market. > > Using the |gigabyte/ga-g41m-es2l| port as a baseline, I have a few quick > questions before I begin: > > 1. > > *GPIO Mapping:* Is dumping registers via |inteltool| the most > reliable method to identify ICH7 GPIO differences from the vendor BIO= S? yes, absolutely. You may want to use the intelp2m tool afterwards to turn the output of inteltool into C code for the gpio.h file. I'm not sure from which comparison you want to draw those differences; I'd start with just dumping the vendor bios' GPIO configuration and then using that as a starting point in coreboot. > > 2. > > *Super I/O Delta:* If the physical Super I/O chip differs from > Gigabyte's ITE IT8718F, which primary configuration files (aside > from |Kconfig| and |devicetree.cb|) require updates? If you're in luck, you'd just adjust devicetree.cb with the correct superio chip (if already supported) and tune some settings. If coreboot does not support your chip already, you may need to write some code inside src/superio/. > > 3. > > *Native Raminit:* Are there any known routing or DIMM slot layout > edge cases that cause native |x4x| raminit to fail on non-reference > boards? Not that I know of. It will likely "just work" if the RAM SPDs are on the default addresses, and if not, you'll figure it out ;). (Worst-case is that raminit fails, but there should be no hardware damage, so you can just try it out.) Happy hacking! Florian -- Florian Jung Development -- TUXEDO Computers GmbH Alter Postweg 101 ~ D-86159 Augsburg -- E-Mail: [email protected] -- https://na01.safelinks.protection.outlook.com/?url=3Dhttp%3A%2F%2Fwww.tuxed= ocomputers.com%2F&data=3D05%7C02%7C%7Cb87aa5fbf4274b8f527808ded3774965%7C84= df9e7fe9f640afb435aaaaaaaaaaaa%7C1%7C0%7C639180706446847593%7CUnknown%7CTWF= pbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIj= oiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=3DUC4POLeqIDxRbnkXxkJ1RCEQeRo= aXo54L5d%2FsNYaQgw%3D&reserved=3D0<http://www.tuxedocomputers.com/> -- Amtsgericht Augsburg: HRB 27755 USt-IdNr.: DE815420876 CEO: Herbert Feiler _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] --_000_EA2P220MB1818F562B16134188FA814939DEB2EA2P220MB1818NAMP_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <html> <head> <meta http-equiv=3D"Content-Type" content=3D"text/html; charset=3Diso-8859-= 1"> </head> <body> <div style=3D"font-family: Aptos, Aptos_MSFontService, -apple-system, Robot= o, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(33, 33, 33);" = dir=3D"auto"> And pls commit the port in the review.coreboot.org</div> <div id=3D"ms-outlook-mobile-body-separator-line" data-applydefaultfontstyl= es=3D"true" dir=3D"auto" style=3D"font-family: Aptos, Aptos_MSFontService, = -apple-system, Roboto, Arial, Helvetica, sans-serif; font-size: 12pt;"> <div style=3D"font-family: Aptos, Aptos_MSFontService, -apple-system, Robot= o, Arial, Helvetica, sans-serif; font-size: 12pt;"> <br> </div> </div> <div id=3D"ms-outlook-mobile-signature" dir=3D"auto" style=3D"font-family: = Aptos, Aptos_MSFontService, -apple-system, Roboto, Arial, Helvetica, sans-s= erif; font-size: 12pt; color: rgb(33, 33, 33);"> <span style=3D"font-family: Aptos, Aptos_MSFontService, -apple-system, Robo= to, Arial, Helvetica, sans-serif; font-size: 12pt; color: rgb(33, 33, 33);"= >Obter o </span><a href=3D"https://aka.ms/AAb9ysg" style=3D"font-family: Aptos, Apto= s_MSFontService, -apple-system, Roboto, Arial, Helvetica, sans-serif; font-= size: 12pt;">Outlook para Android</a></div> <hr style=3D"display:inline-block;width:98%" tabindex=3D"-1"> <div id=3D"divRplyFwdMsg" dir=3D"ltr"><font face=3D"Calibri, sans-serif" st= yle=3D"font-size:11pt" color=3D"#000000"><b>From:</b> Florian Jung via core= boot <[email protected]><br> <b>Sent:</b> Friday, 26 June 2026 08:36:56<br> <b>To:</b> [email protected] <[email protected]><br> <b>Subject:</b> [coreboot] Re: porting coreboot to Enter ATX Motherboard E-= G41D2</font> <div> </div> </div> <div class=3D"BodyFragment"><font size=3D"2"><span style=3D"font-size:11pt;= "> <div class=3D"PlainText">Hi Ashok,<br> <br> Am 26.06.26 um 07:16 schrieb Ashok Arora:<br> > Hi all,<br> > I am planning to port coreboot to the *Enter ATX E-G41D2*(Intel G41 + = <br> > ICH7), a low-cost, popular alternative to the supported *Gigabyte GA- = <br> > G41M-ES2L*in the Indian market.<br> > <br> > Using the |gigabyte/ga-g41m-es2l| port as a baseline, I have a few qui= ck <br> > questions before I begin:<br> > <br> > 1.<br> > <br> > *GPIO Mapping:* Is dumping registers via |inte= ltool| the most<br> > reliable method to identify ICH7 GPIO differen= ces from the vendor BIOS?<br> <br> yes, absolutely. You may want to use the intelp2m tool afterwards to <br> turn the output of inteltool into C code for the gpio.h file.<br> <br> I'm not sure from which comparison you want to draw those differences; <br> I'd start with just dumping the vendor bios' GPIO configuration and then <b= r> using that as a starting point in coreboot.<br> <br> > <br> > 2.<br> > <br> > *Super I/O Delta:* If the physical Super I/O c= hip differs from<br> > Gigabyte's ITE IT8718F, which primary configur= ation files (aside<br> > from |Kconfig| and |devicetree.cb|) require up= dates?<br> <br> If you're in luck, you'd just adjust devicetree.cb with the correct <br> superio chip (if already supported) and tune some settings. If coreboot <br= > does not support your chip already, you may need to write some code <br> inside src/superio/.<br> <br> > <br> > 3.<br> > <br> > *Native Raminit:* Are there any known routing = or DIMM slot layout<br> > edge cases that cause native |x4x| raminit to = fail on non-reference<br> > boards?<br> <br> Not that I know of. It will likely "just work" if the RAM SPDs ar= e on <br> the default addresses, and if not, you'll figure it out ;). (Worst-case <br= > is that raminit fails, but there should be no hardware damage, so you <br> can just try it out.)<br> <br> Happy hacking!<br> Florian<br> <br> <br> -- <br> Florian Jung<br> Development<br> --<br> TUXEDO Computers GmbH<br> Alter Postweg 101 ~ D-86159 Augsburg<br> --<br> E-Mail: [email protected]<br> --<br> <a href=3D"http://www.tuxedocomputers.com/">https://na01.safelinks.protecti= on.outlook.com/?url=3Dhttp%3A%2F%2Fwww.tuxedocomputers.com%2F&data=3D05= %7C02%7C%7Cb87aa5fbf4274b8f527808ded3774965%7C84df9e7fe9f640afb435aaaaaaaaa= aaa%7C1%7C0%7C639180706446847593%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOn= RydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%= 7C0%7C%7C%7C&sdata=3DUC4POLeqIDxRbnkXxkJ1RCEQeRoaXo54L5d%2FsNYaQgw%3D&a= mp;reserved=3D0</a><br> --<br> Amtsgericht Augsburg: HRB 27755<br> USt-IdNr.: DE815420876<br> CEO: Herbert Feiler<br> _______________________________________________<br> coreboot mailing list -- [email protected]<br> To unsubscribe send an email to [email protected]<br> </div> </span></font></div> </body> </html> --_000_EA2P220MB1818F562B16134188FA814939DEB2EA2P220MB1818NAMP_-- --===============6369601862610511392== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ coreboot mailing list -- [email protected] To unsubscribe send an email to [email protected] --===============6369601862610511392==--