Re: porting coreboot to Enter ATX Motherboard E-G41D2

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Hi all,
Thank you for the clarifications. I'll use gpio-scripts instead of intelp2m
and cross-reference the ICH7 datasheet to filter out GPIOs that don't exist
on ICH7. Good to know about the watchdog timer risk in early_init.c too.

The Enter E-G41D2 is on order but delivery is about two weeks out. In the
meantime I've also ordered a Consistent H-81 (Intel H81, LGA1150) which
should arrive sooner. I'm planning to port coreboot to that as well and
test Haswell native raminit using the patch series at
review.coreboot.org/q/topic:haswell-nri, and will report findings back to
the list.

I'll share inteltool and superiotool output from both boards before
proceeding further with either port, and will submit the work to
review.coreboot.org once I have something working.

Best regards,
Ashok

On Sun, Jun 28, 2026 at 2:45=E2=80=AFAM Florian Jung via coreboot <
[email protected]> wrote:

> Hi Ashok,
>
> Am 26.06.26 um 07:16 schrieb Ashok Arora:
> > Hi all,
> > I am planning to port coreboot to the *Enter ATX E-G41D2*(Intel G41 +
> > ICH7), a low-cost, popular alternative to the supported *Gigabyte GA-
> > G41M-ES2L*in the Indian market.
> >
> > Using the |gigabyte/ga-g41m-es2l| port as a baseline, I have a few quic=
k
> > questions before I begin:
> >
> >  1.
> >
> >     *GPIO Mapping:* Is dumping registers via |inteltool| the most
> >     reliable method to identify ICH7 GPIO differences from the vendor
> BIOS?
>
> yes, absolutely. You may want to use the intelp2m tool afterwards to
> turn the output of inteltool into C code for the gpio.h file.
>
> I'm not sure from which comparison you want to draw those differences;
> I'd start with just dumping the vendor bios' GPIO configuration and then
> using that as a starting point in coreboot.
>
> >
> >  2.
> >
> >     *Super I/O Delta:* If the physical Super I/O chip differs from
> >     Gigabyte's ITE IT8718F, which primary configuration files (aside
> >     from |Kconfig| and |devicetree.cb|) require updates?
>
> If you're in luck, you'd just adjust devicetree.cb with the correct
> superio chip (if already supported) and tune some settings. If coreboot
> does not support your chip already, you may need to write some code
> inside src/superio/.
>
> >
> >  3.
> >
> >     *Native Raminit:* Are there any known routing or DIMM slot layout
> >     edge cases that cause native |x4x| raminit to fail on non-reference
> >     boards?
>
> Not that I know of. It will likely "just work" if the RAM SPDs are on
> the default addresses, and if not, you'll figure it out ;). (Worst-case
> is that raminit fails, but there should be no hardware damage, so you
> can just try it out.)
>
> Happy hacking!
> Florian
>
>
> --
> Florian Jung
> Development
> --
> TUXEDO Computers GmbH
> Alter Postweg 101 ~ D-86159 Augsburg
> --
> E-Mail: [email protected]
> --
> www.tuxedocomputers.com
> --
> Amtsgericht Augsburg: HRB 27755
> USt-IdNr.: DE815420876
> CEO: Herbert Feiler
>
> _______________________________________________
> coreboot mailing list -- [email protected]
> To unsubscribe send an email to [email protected]
>

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<div dir=3D"ltr">Hi all,<br>Thank you for the clarifications. I&#39;ll use =
gpio-scripts instead of intelp2m and cross-reference the ICH7 datasheet to =
filter out GPIOs that don&#39;t exist on ICH7. Good to know about the watch=
dog timer risk in early_init.c too.<br><br>The Enter E-G41D2 is on order bu=
t delivery is about two weeks out. In the meantime I&#39;ve also ordered a =
Consistent H-81 (Intel H81, LGA1150) which should arrive sooner. I&#39;m pl=
anning to port coreboot to that as well and test Haswell native raminit usi=
ng the patch series at <a href=3D"http://review.coreboot.org/q/topic:haswel=
l-nri">review.coreboot.org/q/topic:haswell-nri</a>, and will report finding=
s back to the list.<br><br>I&#39;ll share inteltool and superiotool output =
from both boards before proceeding further with either port, and will submi=
t the work to <a href=3D"http://review.coreboot.org">review.coreboot.org</a=
> once I have something working.<br><br>Best regards,<br>Ashok</div><br><di=
v class=3D"gmail_quote gmail_quote_container"><div dir=3D"ltr" class=3D"gma=
il_attr">On Sun, Jun 28, 2026 at 2:45=E2=80=AFAM Florian Jung via coreboot =
&lt;<a href=3D"mailto:[email protected]">[email protected]</a>&gt; =
wrote:<br></div><blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0=
px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hi Ashok,=
<br>
<br>
Am 26.06.26 um 07:16 schrieb Ashok Arora:<br>
&gt; Hi all,<br>
&gt; I am planning to port coreboot to the *Enter ATX E-G41D2*(Intel G41 + =
<br>
&gt; ICH7), a low-cost, popular alternative to the supported *Gigabyte GA- =
<br>
&gt; G41M-ES2L*in the Indian market.<br>
&gt; <br>
&gt; Using the |gigabyte/ga-g41m-es2l| port as a baseline, I have a few qui=
ck <br>
&gt; questions before I begin:<br>
&gt; <br>
&gt;=C2=A0 1.<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0*GPIO Mapping:* Is dumping registers via |inteltool=
| the most<br>
&gt;=C2=A0 =C2=A0 =C2=A0reliable method to identify ICH7 GPIO differences f=
rom the vendor BIOS?<br>
<br>
yes, absolutely. You may want to use the intelp2m tool afterwards to <br>
turn the output of inteltool into C code for the gpio.h file.<br>
<br>
I&#39;m not sure from which comparison you want to draw those differences; =
<br>
I&#39;d start with just dumping the vendor bios&#39; GPIO configuration and=
 then <br>
using that as a starting point in coreboot.<br>
<br>
&gt; <br>
&gt;=C2=A0 2.<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0*Super I/O Delta:* If the physical Super I/O chip d=
iffers from<br>
&gt;=C2=A0 =C2=A0 =C2=A0Gigabyte&#39;s ITE IT8718F, which primary configura=
tion files (aside<br>
&gt;=C2=A0 =C2=A0 =C2=A0from |Kconfig| and |devicetree.cb|) require updates=
?<br>
<br>
If you&#39;re in luck, you&#39;d just adjust devicetree.cb with the correct=
 <br>
superio chip (if already supported) and tune some settings. If coreboot <br=
>
does not support your chip already, you may need to write some code <br>
inside src/superio/.<br>
<br>
&gt; <br>
&gt;=C2=A0 3.<br>
&gt; <br>
&gt;=C2=A0 =C2=A0 =C2=A0*Native Raminit:* Are there any known routing or DI=
MM slot layout<br>
&gt;=C2=A0 =C2=A0 =C2=A0edge cases that cause native |x4x| raminit to fail =
on non-reference<br>
&gt;=C2=A0 =C2=A0 =C2=A0boards?<br>
<br>
Not that I know of. It will likely &quot;just work&quot; if the RAM SPDs ar=
e on <br>
the default addresses, and if not, you&#39;ll figure it out ;). (Worst-case=
 <br>
is that raminit fails, but there should be no hardware damage, so you <br>
can just try it out.)<br>
<br>
Happy hacking!<br>
Florian<br>
<br>
<br>
-- <br>
Florian Jung<br>
Development<br>
--<br>
TUXEDO Computers GmbH<br>
Alter Postweg 101 ~ D-86159 Augsburg<br>
--<br>
E-Mail: <a href=3D"mailto:[email protected]" target=3D"_blank">f.j=
[email protected]</a><br>
--<br>
<a href=3D"http://www.tuxedocomputers.com" rel=3D"noreferrer" target=3D"_bl=
ank">www.tuxedocomputers.com</a><br>
--<br>
Amtsgericht Augsburg: HRB 27755<br>
USt-IdNr.: DE815420876<br>
CEO: Herbert Feiler<br>
<br>
_______________________________________________<br>
coreboot mailing list -- <a href=3D"mailto:[email protected]" target=3D=
"_blank">[email protected]</a><br>
To unsubscribe send an email to <a href=3D"mailto:[email protected]=
rg" target=3D"_blank">[email protected]</a><br>
</blockquote></div>

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