SMP question

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Hi,

First, if this isn't the right place to ask such questions then I'm sorry
for the intrusion.

I'm trying to implement SMP on x86, and ran into a strange issue. I'm using
the same code on BIOS, UEFI and coreboot, the only difference is in the
delay implementation (on BIOS I'm polling the PIT, on UEFI I use BS->Stall,
and on coreboot I use libpayload's ndelay), yet SMP works everywhere except
coreboot.

I don't think the delay implementation should affect this, so my question
is, does coreboot set up APs in any way? I couldn't find such option in
"make menuconfig" (under Chipset / CPU there's only ACPI / xAPIC / x2APIC
options, nothing else, no SMP), and grepping the source came up with
nothing, but I might just missed something.

I'd be very grateful for any pointers. First I want to rule out anything
coreboot related, because that would mean the issue is surely in my code
(likely, but would be great to know for sure).

For the records, my code is here: https://gitlab.com/bztsrc/simpleboot The
BIOS and UEFI code is in src/loader_x86.c, and the coreboot version in
src/loader_cb.c.

Thanks, and again, if this isn't the right place to ask this, I'm sorry to
bother you.
bzt

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<div dir=3D"ltr"><div>Hi,</div><div><br></div><div>First, if this isn&#39;t=
 the right place to ask such questions then I&#39;m sorry for the intrusion=
.</div><div><br></div><div>I&#39;m trying to implement SMP on x86, and ran =
into a strange issue. I&#39;m using the same code on BIOS, UEFI and coreboo=
t, the only difference is in the delay implementation (on BIOS I&#39;m poll=
ing the PIT, on UEFI I use BS-&gt;Stall, and on coreboot I use libpayload&#=
39;s ndelay), yet SMP works everywhere except coreboot.</div><div><br></div=
><div>I don&#39;t think the delay implementation should affect this, so my =
question is, does coreboot set up APs in any way? I couldn&#39;t find such =
option in &quot;make menuconfig&quot; (under Chipset / CPU there&#39;s only=
 ACPI / xAPIC / x2APIC options, nothing else, no SMP), and grepping the sou=
rce came up with nothing, but I might just missed something.</div><div><br>=
</div><div></div><div>I&#39;d be very grateful for any pointers. First I wa=
nt to rule out anything coreboot related, because that would mean the issue=
 is surely in my code (likely, but would be great to know for sure).</div><=
div><br></div><div>For the records, my code is here: <a href=3D"https://git=
lab.com/bztsrc/simpleboot">https://gitlab.com/bztsrc/simpleboot</a> The BIO=
S and UEFI code is in src/loader_x86.c, and the coreboot version in src/loa=
der_cb.c.</div><div><br></div><div>Thanks, and again, if this isn&#39;t the=
 right place to ask this, I&#39;m sorry to bother you.</div><div>bzt</div><=
div><br></div></div>

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