[Git][xorg-team/lib/mesa][debian-unstable] 102 commits: docs: add sha sum for 26.0.0
"Timo Aaltonen (@tjaalton)" <[email protected]>
| Newsgroups | gmane.linux.debian.devel.x |
|---|---|
| Message-ID | <[email protected]> |
Timo Aaltonen pushed to branch debian-unstable at X Strike Force / lib / mesa
Commits:
8794fced by Eric Engestrom at 2026-02-11T19:19:12+01:00
docs: add sha sum for 26.0.0
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572e31b4 by Timo Aaltonen at 2026-02-16T10:55:03+02:00
rules: Enable imagination vulkan driver on arm/loong/riscv.
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127356fc by Timo Aaltonen at 2026-02-16T11:28:22+02:00
control, rules: Drop armel and mips64el.
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4e6e71db by Timo Aaltonen at 2026-02-16T11:29:06+02:00
rules: Add riscv64 to VALGRIND_ARCHS.
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925c7c20 by Timo Aaltonen at 2026-02-16T11:32:41+02:00
control: Add riscv64 to mesa-drm-shim archs.
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e5fb4a06 by Eric Engestrom at 2026-02-25T14:22:19+01:00
.pick_status.json: Update to 03d2cc2b2ae5341409ee1fab74e98134a6df0511
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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9a0d13be by Eric Engestrom at 2026-02-25T14:22:19+01:00
bin/gen_release_notes: fix support for python 3.14
There is no default even loop anymore, we need to make one if we want
one now.
Cc: mesa-stable
(cherry picked from commit c7603a11deb55c2f9640725dbcdbf51ee6335bea)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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547fd52a by Eric Engestrom at 2026-02-25T14:22:19+01:00
pick-ui: add `Backport-to: *` as a synonym to `Cc: mesa-stable`
(cherry picked from commit b2d99b93780a047356603ae8058f88e349d1bfde)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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14c7d820 by Matt Turner at 2026-02-25T14:22:19+01:00
brw/cse: fix `operands_match` corrupting non-IMM register data
The MUL case in `operands_match` was reading and writing the `.f` union
member unconditionally, even when the register's `.file != IMM`. In that
case `.f` aliases the struct containing `.nr`/`.swizzle`/etc, so the
`fabsf()` call could corrupt the `.nr` by clearing bit 31.
Guard all `.f` accesses with `.file == IMM` checks.
Fixes: 47c4b385407 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
(cherry picked from commit f5e0f632168929684653677738adbfcc2679e76e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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2b221e5a by Matt Turner at 2026-02-25T14:22:20+01:00
brw/cse: use copies in `operands_match` instead of in-place modification
`operands_match` was modifying instruction source operands in-place
(through the `brw_reg *src` pointer member) and relying on a
save/restore pattern to undo the modifications. Work on local copies
instead, which is simpler and avoids mutating shared state in a
comparison function.
Fixes: 47c4b385407 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
(cherry picked from commit b302faad8b6878811758eef087cee7228e9801a0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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03e6f285 by Matt Turner at 2026-02-25T14:22:20+01:00
elk/cse: fix `operands_match` corrupting non-IMM register data
The MUL case in `operands_match` was reading and writing the `.f` union
member unconditionally, even when the register's `.file != IMM`. In that
case `.f` aliases the struct containing `.nr`/`.swizzle`/etc, so the
`fabsf()` call could corrupt the `.nr` by clearing bit 31.
Guard all `.f` accesses with `.file == IMM` checks.
Fixes: 47c4b385407 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
(cherry picked from commit 93f39f87c46976e7b05b194fd805b750c89f001e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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2c250e62 by Matt Turner at 2026-02-25T14:22:20+01:00
elk/cse: use copies in `operands_match` instead of in-place modification
`operands_match` was modifying instruction source operands in-place
(through the `elk_fs_reg *src` pointer member) and relying on a
save/restore pattern to undo the modifications. Work on local copies
instead, which is simpler and avoids mutating shared state in a
comparison function.
Fixes: 47c4b385407 ("i965/fs: Allow CSE to handle MULs with negated arguments.")
(cherry picked from commit 14c65322e8504c498115fe6c11b095d555e03f2d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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6dbd6ee9 by Juston Li at 2026-02-25T14:22:20+01:00
anv: set missing protected bit for protected depth/stencil surfaces
This bit is set in mocs for other protected attachment types by
anv_image_fill_surface_state() however was ommited for depth/stencil
attachments here.
Without the protected bit set, it causes heavy black artifacting when
attaching a protected depth attachment image to a framebuffer.
Fixes: 794b0496e94 ("anv: enable protected memory")
Signed-off-by: Juston Li <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit f84ed620c26ea3d74ec792ce6c70ad628f667d40)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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2abdb028 by Lionel Landwerlin at 2026-02-25T14:22:20+01:00
anv: flush render caches on first pipeline select
Given a situation like this :
- CB_A: begin, renderDepthA, end
- CB_B: begin, computeA, barrier (depth), computeB, end
The depth cache is not being flushed between renderDepthA & computeB
because :
- it's not flushed at the end of CB_A (it's not required)
- when CB_B starts, we're still on GFX pipeline mode but do not
flush render caches because pipeline mode is unknown
- when barrier is CB_B is executed, we're already in compute
pipeline mode and HW cannot flush depth.
The fix is to flush RT/depth cached when switching from unknown
pipeline mode any pipeline mode.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: e6dae6ef5fc ("vulkan: Optimize implicit end_subpass barrier")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14816
Reviewed-by: José Roberto de Souza <[email protected]>
Tested-by: David Gow <[email protected]>
(cherry picked from commit 888ac904a34da1e467a3943d555336edda444ada)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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f8ce75c4 by Konstantin Seurer at 2026-02-25T14:22:20+01:00
radv: Fix setting the viewport for depth stencil FS resolves
Fixes: 704fbbb ("radv/meta: rework depth/stencil resolves using graphics")
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit f574de2249a9b085786f7be1af2478cb4c0066a7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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12da136c by Lionel Landwerlin at 2026-02-25T14:22:20+01:00
anv: fix nested command buffer relocations
When executing 3 command buffers :
vkCmdExecuteCommands(CB_B, CB_C);
vkCmdExecuteCommands(CB_A, CB_B);
vkQueueSubmit(CB_A);
We're not transfering correctly the relocations of CB_C from CB_B to
CB_A.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit e64889635c554248cb5b1ccf6bf9a57ea259a88c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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af97f7fe by Lionel Landwerlin at 2026-02-25T14:22:20+01:00
anv: add missing constant cache invalidation for descriptor buffers
A descriptor buffer promoted to push constants requires a constant
cache invalidation if it is modified on the device.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 42b70cf05aad4feab08bcddbe27de47105d7c36a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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1994d935 by Lionel Landwerlin at 2026-02-25T14:22:20+01:00
isl: fix 32bit math with 4GB buffer size
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit d9569571537e5f252b3893cbe2c4bb6fb1bede1c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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4229b577 by Aitor Camacho at 2026-02-25T14:22:20+01:00
wsi/metal: Expose additional color spaces if instance extension enabled
Caught through VVL test NegativeWsi.SwapchainImageFormatList. The test
would try to create a swapchain with a color space from
VK_EXT_swapchain_colorspace without enabling the extension. This is
because wsi would expose those color spaces even when the extension was
not enabled.
Fixes: fd045ac99ce ("wsi/metal: add support for color spaces")
Reviewed-by: Yiwei Zhang <[email protected]>
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit e6f118f12b9405d0562343e34a286842fc9ffc69)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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88e238de by Eric Engestrom at 2026-02-25T14:22:20+01:00
.pick_status.json: Mark 7dd7731ac710b0c7213f6bb466b33f62eca80604 as denominated
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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a2ad1789 by Samuel Pitoiset at 2026-02-25T14:22:20+01:00
ac,radv,radeonsi: use correct swizzle/pitch for depth-only images with SDMA
This fixes new VKCTS coverage
dEQP-VK.api.copy_and_blit.core.use_after_copy.*.
is_stencil isn't set for RadeonSI because it doesn't do SDMA copies
with Z/S.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 1be4ffdff926597c82a6482b482e4f1d8e74f038)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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7fda7855 by Daniel Schürmann at 2026-02-25T14:22:20+01:00
nir/clone: Fix cloning indirect call instructions
Fixes: bb40284f76e1b2151b79b4bfa015110f8239144e ('nir: Add indirect calls')
(cherry picked from commit 88b4221519438dc66523c7832d6e5037173fa72f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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6278aa10 by Anna Maniscalco at 2026-02-25T14:22:20+01:00
freedreno/common: set has_astc_hdr true for a7xx targets
Fixes: dc07473524af ("freedreno/fdl: add astc hdr formats")
Reviewed-by: Danylo Piliaiev <[email protected]>
(cherry picked from commit e959dd0dd7b5fc7b168c45b34b8892a3eb6876df)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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806f0a35 by Alyssa Rosenzweig at 2026-02-25T14:22:20+01:00
brw: drop buggy SLM optimization
This was incorrect for OpenCL due to the possibility of variable shared memory
existing despite shared_size == 0. Fortunately the optimization it was trying to
do should be done in NIR via nir_opt_barrier_modes so we can just drop the brw
code and move on with our merry lives. Fixes OpenCL tests on Iris:
non_uniform_work_group non_uniform_3d_barriers
basic async_strided_copy_local_to_global
Cc: mesa-stable
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit bd5ebbb2f8bcfcd178d8bc62a55ab97abb57e140)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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5048a2ed by Jesse Natalie at 2026-02-25T14:22:20+01:00
meson: Include DirectX-Headers dependency for all VK Windows builds
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14839
Cc: mesa-stable
Reviewed-by: Eric Engestrom <[email protected]>
(cherry picked from commit f0066a3150d629bd6e4ca7f365cd9154c93ba1c9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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978fd42b by Ian Romanick at 2026-02-25T14:22:20+01:00
spirv: Use STACK_ARRAY instead of NIR_VLA
The number of fields comes from the shader, so it could be a value large
enough that using alloca would be problematic.
Fixes: 2a023f30a64 ("nir/spirv: Add basic support for types")
Reviewed-by: Caio Oliveira <[email protected]>
Reviewed-by: Ryan Neph <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 3da828d2dd12e20ba2afc152db8d7236c7a48c13)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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45ce75f3 by Ian Romanick at 2026-02-25T14:22:20+01:00
nir: Use STACK_ARRAY instead of NIR_VLA
The number of fields comes from the shader, so it could be a value large
enough that using alloca would be problematic.
Fixes: c11833ab24d ("nir,spirv: Rework function calls")
Reviewed-by: Caio Oliveira <[email protected]>
Reviewed-by: Ryan Neph <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 9017d37e84771f921a63676dd8b955df9ef20f29)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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3ffe4b25 by Konstantin Seurer at 2026-02-25T14:22:20+01:00
vulkan/cmd_queue: Fixup stride for multi draws
Copying the draw infos packs them so the stride needs to be set to the
struct size.
cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <[email protected]>
(cherry picked from commit be5ab80de15a642d537a5072bc341c38293a1baa)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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2874160c by Ian Romanick at 2026-02-25T14:22:20+01:00
brw: Call nir_opt_algebraic_late in brw_nir_create_raygen_trampoline
Make sure that lowering undone in brw_nir_optimize are reapplied.
No shader-db changes on any Intel platform.
Why are there fossil-db changes on platforms that don't support ray tracing?
Lunar Lake
Totals:
Instrs: 926636441 -> 926636313 (-0.00%); split: -0.00%, +0.00%
Send messages: 41510729 -> 41510723 (-0.00%); split: -0.00%, +0.00%
Cycle count: 104509492613 -> 104509490569 (-0.00%); split: -0.00%, +0.00%
Max live registers: 193792922 -> 193792890 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 150091934 -> 150092170 (+0.00%); split: -0.00%, +0.00%
Totals from 10 (0.00% of 2020428) affected shaders:
Instrs: 8142 -> 8014 (-1.57%); split: -3.14%, +1.57%
Send messages: 192 -> 186 (-3.12%); split: -7.29%, +4.17%
Cycle count: 131892 -> 129848 (-1.55%); split: -6.93%, +5.38%
Max live registers: 1442 -> 1410 (-2.22%); split: -3.05%, +0.83%
Non SSA regs after NIR: 950 -> 1186 (+24.84%); split: -26.95%, +51.79%
Meteor Lake
Totals:
Instrs: 1000805547 -> 1000805543 (-0.00%); split: -0.00%, +0.00%
Cycle count: 93131592265 -> 93131619619 (+0.00%); split: -0.00%, +0.00%
Max live registers: 122081268 -> 122081244 (-0.00%); split: -0.00%, +0.00%
Totals from 16 (0.00% of 2286241) affected shaders:
Instrs: 18652 -> 18648 (-0.02%); split: -1.39%, +1.37%
Cycle count: 369520 -> 396874 (+7.40%); split: -2.94%, +10.34%
Max live registers: 1350 -> 1326 (-1.78%); split: -4.15%, +2.37%
DG2
Totals:
Instrs: 999834626 -> 999834651 (+0.00%); split: -0.00%, +0.00%
Send messages: 45719398 -> 45719403 (+0.00%); split: -0.00%, +0.00%
Cycle count: 93118238139 -> 93118269557 (+0.00%); split: -0.00%, +0.00%
Max live registers: 122098944 -> 122098936 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 169413734 -> 169413661 (-0.00%); split: -0.00%, +0.00%
Totals from 13 (0.00% of 2286795) affected shaders:
Instrs: 18799 -> 18824 (+0.13%); split: -1.04%, +1.18%
Send messages: 492 -> 497 (+1.02%); split: -2.44%, +3.46%
Cycle count: 352838 -> 384256 (+8.90%); split: -1.08%, +9.98%
Max live registers: 1237 -> 1229 (-0.65%); split: -2.91%, +2.26%
Non SSA regs after NIR: 2191 -> 2118 (-3.33%); split: -20.86%, +17.53%
Tiger Lake
Totals:
Instrs: 1011816778 -> 1011816714 (-0.00%); split: -0.00%, +0.00%
Send messages: 46515289 -> 46515285 (-0.00%); split: -0.00%, +0.00%
Cycle count: 85148902406 -> 85148894668 (-0.00%); split: -0.00%, +0.00%
Max live registers: 122362180 -> 122362172 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 38036160 -> 38036176 (+0.00%)
Non SSA regs after NIR: 160317521 -> 160317649 (+0.00%); split: -0.00%, +0.00%
Totals from 6 (0.00% of 2282318) affected shaders:
Instrs: 9204 -> 9140 (-0.70%); split: -1.43%, +0.74%
Send messages: 258 -> 254 (-1.55%); split: -3.10%, +1.55%
Cycle count: 287652 -> 279914 (-2.69%); split: -3.29%, +0.60%
Max live registers: 552 -> 544 (-1.45%); split: -2.90%, +1.45%
Max dispatch width: 48 -> 64 (+33.33%)
Non SSA regs after NIR: 914 -> 1042 (+14.00%); split: -14.00%, +28.01%
Ice Lake
Totals:
Instrs: 1012203285 -> 1012203249 (-0.00%); split: -0.00%, +0.00%
Send messages: 47358859 -> 47358858 (-0.00%); split: -0.00%, +0.00%
Cycle count: 85112165276 -> 85112171905 (+0.00%); split: -0.00%, +0.00%
Max live registers: 125545002 -> 125544992 (-0.00%); split: -0.00%, +0.00%
Max dispatch width: 41335696 -> 41335656 (-0.00%)
Non SSA regs after NIR: 166448597 -> 166448602 (+0.00%); split: -0.00%, +0.00%
Totals from 13 (0.00% of 2335519) affected shaders:
Instrs: 16486 -> 16450 (-0.22%); split: -1.67%, +1.46%
Send messages: 368 -> 367 (-0.27%); split: -4.89%, +4.62%
Cycle count: 347643 -> 354272 (+1.91%); split: -1.34%, +3.25%
Max live registers: 1104 -> 1094 (-0.91%); split: -3.80%, +2.90%
Max dispatch width: 192 -> 152 (-20.83%)
Non SSA regs after NIR: 2100 -> 2105 (+0.24%); split: -21.76%, +22.00%
Skylake
Totals:
Instrs: 504548665 -> 504548057 (-0.00%); split: -0.00%, +0.00%
Send messages: 24479148 -> 24479118 (-0.00%); split: -0.00%, +0.00%
Cycle count: 57575198140 -> 57575179256 (-0.00%); split: -0.00%, +0.00%
Max live registers: 85570671 -> 85570575 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 85097646 -> 85098486 (+0.00%); split: -0.00%, +0.00%
Totals from 22 (0.00% of 1703671) affected shaders:
Instrs: 19866 -> 19258 (-3.06%); split: -3.72%, +0.66%
Send messages: 464 -> 434 (-6.47%); split: -8.19%, +1.72%
Cycle count: 250854 -> 231970 (-7.53%); split: -9.23%, +1.70%
Max live registers: 2024 -> 1928 (-4.74%); split: -5.53%, +0.79%
Non SSA regs after NIR: 2498 -> 3338 (+33.63%); split: -8.33%, +41.95%
Fixes: 442daeb54a2 ("nir/opt_algebraic: use fcanonicalize")
Reviewed-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit 5af0b8bd09f6e07d9a069ddbd93eeffd90ba1906)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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1f65b768 by Ian Romanick at 2026-02-25T14:22:20+01:00
brw: Call nir_opt_algebraic_late later in brw_postprocess_nir_opts
Move the call to nir_opt_algebraic_late after the last time
brw_nir_optimize might be called. nir_opt_algebraic_distribute_src_mods
works together with the late algebraic optimizations, so move it also.
shader-db:
Lunar Lake
total instructions in shared programs: 17081222 -> 17080842 (<.01%)
instructions in affected programs: 419931 -> 419551 (-0.09%)
helped: 545 / HURT: 826
total cycles in shared programs: 878437752 -> 879236226 (0.09%)
cycles in affected programs: 506003142 -> 506801616 (0.16%)
helped: 3091 / HURT: 3189
LOST: 18
GAINED: 16
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total instructions in shared programs: 19994270 -> 19993231 (<.01%)
instructions in affected programs: 490499 -> 489460 (-0.21%)
helped: 660 / HURT: 800
total cycles in shared programs: 882498776 -> 882834186 (0.04%)
cycles in affected programs: 477858602 -> 478194012 (0.07%)
helped: 3458 / HURT: 3564
total fills in shared programs: 4371 -> 4370 (-0.02%)
fills in affected programs: 7 -> 6 (-14.29%)
helped: 1 / HURT: 0
LOST: 28
GAINED: 10
Tiger Lake, Ice Lake, and Skylake had similar results. (Tiger Lake shown)
total instructions in shared programs: 19943849 -> 19942782 (<.01%)
instructions in affected programs: 467384 -> 466317 (-0.23%)
helped: 655 / HURT: 796
total cycles in shared programs: 860085674 -> 861410289 (0.15%)
cycles in affected programs: 426900998 -> 428225613 (0.31%)
helped: 3250 / HURT: 3441
LOST: 19
GAINED: 14
fossil-db:
Lunar Lake
Totals:
Instrs: 926472091 -> 926204838 (-0.03%); split: -0.04%, +0.01%
CodeSize: 14845921056 -> 14842776112 (-0.02%); split: -0.10%, +0.08%
Send messages: 41459570 -> 41459574 (+0.00%); split: -0.00%, +0.00%
Cycle count: 104481085069 -> 104583692712 (+0.10%); split: -0.14%, +0.24%
Spill count: 3454651 -> 3457340 (+0.08%); split: -0.15%, +0.23%
Fill count: 4958779 -> 4958487 (-0.01%); split: -0.46%, +0.45%
Max live registers: 193805970 -> 193839002 (+0.02%); split: -0.00%, +0.02%
Max dispatch width: 49114416 -> 49113776 (-0.00%); split: +0.01%, -0.01%
Non SSA regs after NIR: 142953905 -> 142800740 (-0.11%); split: -0.12%, +0.01%
Totals from 420256 (20.80% of 2020128) affected shaders:
Instrs: 448571327 -> 448304074 (-0.06%); split: -0.09%, +0.03%
CodeSize: 7312002800 -> 7308857856 (-0.04%); split: -0.21%, +0.17%
Send messages: 17716494 -> 17716498 (+0.00%); split: -0.00%, +0.00%
Cycle count: 52178854998 -> 52281462641 (+0.20%); split: -0.28%, +0.48%
Spill count: 2945654 -> 2948343 (+0.09%); split: -0.17%, +0.26%
Fill count: 4404768 -> 4404476 (-0.01%); split: -0.51%, +0.51%
Max live registers: 60875448 -> 60908480 (+0.05%); split: -0.01%, +0.06%
Max dispatch width: 9455280 -> 9454640 (-0.01%); split: +0.04%, -0.04%
Non SSA regs after NIR: 60542740 -> 60389575 (-0.25%); split: -0.28%, +0.02%
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
Totals:
Instrs: 1000081384 -> 999726726 (-0.04%); split: -0.05%, +0.01%
CodeSize: 16764458080 -> 16761624256 (-0.02%); split: -0.09%, +0.07%
Subgroup size: 27599528 -> 27599544 (+0.00%)
Send messages: 45538933 -> 45538951 (+0.00%); split: -0.00%, +0.00%
Cycle count: 93303830912 -> 93370118192 (+0.07%); split: -0.19%, +0.26%
Spill count: 3739306 -> 3739719 (+0.01%); split: -0.22%, +0.23%
Fill count: 5089719 -> 5083626 (-0.12%); split: -0.56%, +0.44%
Max live registers: 122041364 -> 122055848 (+0.01%); split: -0.00%, +0.01%
Max dispatch width: 38117296 -> 38127200 (+0.03%); split: +0.06%, -0.03%
Non SSA regs after NIR: 164296197 -> 164299306 (+0.00%); split: -0.01%, +0.01%
Totals from 338754 (14.82% of 2285730) affected shaders:
Instrs: 452723479 -> 452368821 (-0.08%); split: -0.10%, +0.03%
CodeSize: 7861878032 -> 7859044208 (-0.04%); split: -0.19%, +0.16%
Subgroup size: 16 -> 32 (+100.00%)
Send messages: 17050010 -> 17050028 (+0.00%); split: -0.00%, +0.00%
Cycle count: 52881801997 -> 52948089277 (+0.13%); split: -0.33%, +0.46%
Spill count: 3271458 -> 3271871 (+0.01%); split: -0.25%, +0.26%
Fill count: 4628422 -> 4622329 (-0.13%); split: -0.61%, +0.48%
Max live registers: 30738902 -> 30753386 (+0.05%); split: -0.01%, +0.06%
Max dispatch width: 4787264 -> 4797168 (+0.21%); split: +0.47%, -0.26%
Non SSA regs after NIR: 61748026 -> 61751135 (+0.01%); split: -0.03%, +0.03%
Tiger Lake
Totals:
Instrs: 1011068379 -> 1010977290 (-0.01%); split: -0.03%, +0.02%
CodeSize: 14197751744 -> 14197683040 (-0.00%); split: -0.07%, +0.07%
Send messages: 46431228 -> 46431220 (-0.00%); split: -0.00%, +0.00%
Cycle count: 85066526419 -> 85085088071 (+0.02%); split: -0.16%, +0.18%
Spill count: 3853750 -> 3855185 (+0.04%); split: -0.15%, +0.19%
Fill count: 6716746 -> 6719594 (+0.04%); split: -0.25%, +0.29%
Max live registers: 122307387 -> 122326083 (+0.02%); split: -0.00%, +0.02%
Max dispatch width: 38009632 -> 38003280 (-0.02%); split: +0.03%, -0.05%
Non SSA regs after NIR: 158403572 -> 158415390 (+0.01%); split: -0.01%, +0.02%
Totals from 277728 (12.17% of 2281577) affected shaders:
Instrs: 349206856 -> 349115767 (-0.03%); split: -0.07%, +0.05%
CodeSize: 5042621104 -> 5042552400 (-0.00%); split: -0.20%, +0.20%
Send messages: 13132243 -> 13132235 (-0.00%); split: -0.00%, +0.00%
Cycle count: 36183327716 -> 36201889368 (+0.05%); split: -0.38%, +0.43%
Spill count: 2210072 -> 2211507 (+0.06%); split: -0.26%, +0.33%
Fill count: 4188439 -> 4191287 (+0.07%); split: -0.39%, +0.46%
Max live registers: 24956695 -> 24975391 (+0.07%); split: -0.02%, +0.09%
Max dispatch width: 3948832 -> 3942480 (-0.16%); split: +0.32%, -0.48%
Non SSA regs after NIR: 45616425 -> 45628243 (+0.03%); split: -0.04%, +0.06%
Ice Lake
Totals:
Instrs: 1009584306 -> 1009411757 (-0.02%); split: -0.02%, +0.01%
CodeSize: 12593466880 -> 12592958096 (-0.00%); split: -0.01%, +0.01%
Send messages: 47274203 -> 47274171 (-0.00%); split: -0.00%, +0.00%
Cycle count: 84920281455 -> 84914027301 (-0.01%); split: -0.05%, +0.04%
Spill count: 2988523 -> 2986191 (-0.08%); split: -0.14%, +0.07%
Fill count: 5296078 -> 5288737 (-0.14%); split: -0.21%, +0.07%
Max live registers: 125429384 -> 125444786 (+0.01%); split: -0.00%, +0.02%
Max dispatch width: 41269072 -> 41267312 (-0.00%); split: +0.03%, -0.03%
Non SSA regs after NIR: 163223895 -> 163236623 (+0.01%); split: -0.01%, +0.02%
Totals from 243818 (10.45% of 2334244) affected shaders:
Instrs: 296953759 -> 296781210 (-0.06%); split: -0.08%, +0.02%
CodeSize: 3643224480 -> 3642715696 (-0.01%); split: -0.04%, +0.03%
Send messages: 11518671 -> 11518639 (-0.00%); split: -0.00%, +0.00%
Cycle count: 33065548412 -> 33059294258 (-0.02%); split: -0.13%, +0.11%
Spill count: 1346515 -> 1344183 (-0.17%); split: -0.32%, +0.15%
Fill count: 2537906 -> 2530565 (-0.29%); split: -0.43%, +0.14%
Max live registers: 21476776 -> 21492178 (+0.07%); split: -0.02%, +0.09%
Max dispatch width: 3727288 -> 3725528 (-0.05%); split: +0.31%, -0.35%
Non SSA regs after NIR: 41050474 -> 41063202 (+0.03%); split: -0.04%, +0.07%
Skylake
Totals:
Instrs: 513573157 -> 513462971 (-0.02%); split: -0.02%, +0.00%
CodeSize: 5950280672 -> 5950001392 (-0.00%); split: -0.01%, +0.00%
Send messages: 24909757 -> 24909758 (+0.00%); split: -0.00%, +0.00%
Cycle count: 57636102242 -> 57634726342 (-0.00%); split: -0.03%, +0.03%
Spill count: 627286 -> 627241 (-0.01%); split: -0.01%, +0.00%
Fill count: 837888 -> 837804 (-0.01%); split: -0.01%, +0.00%
Max live registers: 87272271 -> 87284192 (+0.01%); split: -0.00%, +0.02%
Max dispatch width: 32278832 -> 32271800 (-0.02%); split: +0.02%, -0.04%
Non SSA regs after NIR: 87387713 -> 87387614 (-0.00%); split: -0.00%, +0.00%
Totals from 177432 (10.30% of 1722906) affected shaders:
Instrs: 127170648 -> 127060462 (-0.09%); split: -0.10%, +0.01%
CodeSize: 1443406368 -> 1443127088 (-0.02%); split: -0.03%, +0.01%
Send messages: 5444220 -> 5444221 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15423028495 -> 15421652595 (-0.01%); split: -0.10%, +0.10%
Spill count: 235844 -> 235799 (-0.02%); split: -0.03%, +0.01%
Fill count: 333783 -> 333699 (-0.03%); split: -0.03%, +0.01%
Max live registers: 13765573 -> 13777494 (+0.09%); split: -0.01%, +0.10%
Max dispatch width: 3086880 -> 3079848 (-0.23%); split: +0.24%, -0.47%
Non SSA regs after NIR: 17623772 -> 17623673 (-0.00%); split: -0.00%, +0.00%
Fixes: 442daeb54a2 ("nir/opt_algebraic: use fcanonicalize")
Reviewed-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit 11b96a84b0d0b2471c04c270b8800e77ccbcbf0c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
0710d042 by Ian Romanick at 2026-02-25T14:22:20+01:00
elk: Call nir_opt_algebraic_late in elk_postprocess_nir
Make sure that lowering undone in elk_nir_optimize are reapplied.
No shader-db or fossil-db changes on any Intel platform. This is most
likely to impact either Gfx8 on ANV or Gfx7.5 on HASVK. I don't
fossil-db test either of those platforms.
I tried doing a similar thing here as is done in BRW (previous commit),
but that caused a couple Haswell shaders to fall off a performance
cliff:
total spills in shared programs: 8247 -> 8311 (0.78%)
spills in affected programs: 6 -> 70 (1066.67%)
helped: 0 / HURT: 2
total fills in shared programs: 8558 -> 8910 (4.11%)
fills in affected programs: 6 -> 358 (5866.67%)
helped: 0 / HURT: 2
Fixes: 442daeb54a2 ("nir/opt_algebraic: use fcanonicalize")
Reviewed-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit df704bd38e77b1cea53d6396e03198cd58f8ad51)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
d7fa6a4d by Timothy Arceri at 2026-02-25T14:22:21+01:00
mesa: add _mesa_lookup_state_param_idx() helper
This will be used in the following patch.
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Mike Blumenkrantz <[email protected]>
(cherry picked from commit c3aae0714c65e359e7dc240fe040706beed1859d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
6fb7a07c by Timothy Arceri at 2026-02-25T14:22:21+01:00
st/glsl_to_nir: make sure the variant has the correct locations set
For drivers that set allow_st_finalize_nir_twice locations are set
when the variable is created. But for variants here we update the
locations in case parameter opt pass or something else changed the
location.
Fixes: 891d46f517ce ("st/glsl_to_nir: dont add duplicate state tokens")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14837
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Mike Blumenkrantz <[email protected]>
(cherry picked from commit a6fcc2835ead0282c2bb6c29e0eed3711b2ec6d1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
7c0b97be by Yiwei Zhang at 2026-02-25T14:22:21+01:00
venus: workaround a gcc-15 dead store elimination (DSE) bug
No issue with clang or gcc-14.x (or earlier versions). The issue only
shows up since gcc-15.1. The compiler somehow fails to consider those
cs helpers dereferencing the pointer from the pNext chain for reads,
and thus has falsely optimized away the pNext store. This change works
around this with a no-op memory clobber.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13242
Cc: mesa-stable
(cherry picked from commit b0397b967d9ca826e34745cebd26bfa82f1b3252)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
98e2234e by Pavel Ondračka at 2026-02-25T14:22:21+01:00
r300: align macro-tiled stride-addressed textures in X
Odd macro-tile counts in X trigger flaky rendering/readback in
parallel stress runs with macro-tiled NPOT textures (for example
piglit draw-pixel-with-texture -auto -fbo).
When a texture is macro-tiled and uses stride addressing, align the
width to two macro tiles. This keeps the stride at an even number of
macro tiles in X and avoids the corruption without disabling
macrotiling.
I was not able to find anything about this in the docs.
Cc: mesa-stable
(cherry picked from commit 0763fb947a338c50eef69f5af6d9a20204ef4b1b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
43b9a2ea by Lars-Ivar Hesselberg Simonsen at 2026-02-25T14:22:21+01:00
panvk: Fix dcd_flags1 dirty bit
dcd_flags1 was not counted as dirty in case the color attachment map was
updated. This could lead to an outdated value for render_target_mask.
Fixes: a4670a67e0e ("panvk/csf: Set the correct DCD_FLAGS_1.render_rarget_mask")
Reviewed-by: Christoph Pillmayer <[email protected]>
Acked-by: Erik Faye-Lund <[email protected]>
(cherry picked from commit 75242b18623aa7316520e6e81fdb8b9c7a3ec43b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
11db64a7 by Lars-Ivar Hesselberg Simonsen at 2026-02-25T14:22:21+01:00
pan/genxml/v13: Fix HSR Prepass typo
Fixes: ece01443e18 ("pan/genxml: Add v13 definition")
Reviewed-by: Christoph Pillmayer <[email protected]>
Acked-by: Erik Faye-Lund <[email protected]>
(cherry picked from commit 71500a32fad8c109a6737c7492e3c15892fd8424)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
96ee7156 by Ryan Zhang at 2026-02-25T14:22:21+01:00
panvk: guard against NULL pointers to avoid crash
Vkcts simulate_oom caselist try to alloc fail manual
which caused the panvk crash. We should guard driver
cannot access null pointor.
Fixes: 598a8d9d11f ("panvk: Collect allocated push
sets at the command level")
Fixed:
dEQP-VK.wsi.wayland.swapchain.simulate_oom.*
Signed-off-by: Ryan Zhang <[email protected]>
Reviewed-by: Erik Faye-Lund <[email protected]>
Reviewed-by: Yiwei Zhang <[email protected]>
(cherry picked from commit 418e6c4ed980f7e33dc49731bf6aad8bf1414db3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
f60b93b4 by Wei Hao at 2026-02-25T14:22:21+01:00
radeonsi: fix threaded shader compilation finishing after context is destroyed
Reviewed-by: Marek Olšák <[email protected]>
(cherry picked from commit ec6d0773517bd083c494530a25c47f9fcce4b8ca)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
372c7545 by Jianxun Zhang at 2026-02-25T14:22:21+01:00
anv: Limit modifier disabling workaround to specific GTK versions
The issue caused us to put a switch to disable (Xe2) drm modifers
in 2418c9153758783d250982f9b84fb65b1b484294 is fixed in GTK 4.20.3,
so we can enable the modifiers with this and newer GTK releases.
GTK https://gitlab.gnome.org/GNOME/gtk/-/merge_requests/9164:
b2a42d5a6e Revert "vulkan: Wait for device to be idle before
create/recreating swapchain"
270735a151 vulkan: Rework swapchain present implementation
The hex values represent the GTK version range: [4.0.0, 4.20.2] for
VK_MAKE_VERSION(), refer to:
f493f5c88d9c243d300aaffe059d59e3b1c5b070
Cc: mesa-stable
Signed-off-by: Jianxun Zhang <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
(cherry picked from commit df7d333656932dea4622e6f648eaef31b2d83f1a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
0f21dc1b by Pavel Ondračka at 2026-02-25T14:22:21+01:00
mesa: implement FRAMEBUFFER_RENDERABLE internalformat query
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Erik Faye-Lund <[email protected]>
Cc: mesa-stable
(cherry picked from commit 2b76f2e4a77dee86ddd8a163b452cfcce52b8c6a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
37a269e3 by Janne Grunau at 2026-02-25T14:22:21+01:00
asahi: Use GPU for buffer copies in resource_copy_region()
Use a compute shader to copy PIPE_BUFFERs. Based on hk's hk_cmd_copy().
For large copy sizes (>= 128MB) it achieves 3/4 of the available memory
bandwidth on a M1 Ultra (G13D). `gpu-ratemeter gl.bufbw` reports
~625 GB/s for 256MB buffer size. Apple specifies the memory bandwidth of
the M1 Ultra with 819.2 GB/s.
Signed-off-by: Janne Grunau <[email protected]>
(cherry picked from commit 3f5497ded8055e0c241f4a87e2f10907be87e02c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
1ce5b5b3 by Janne Grunau at 2026-02-25T14:22:21+01:00
asahi: Implement clear_buffer using libagx_fill*
Use either libagx_fill_uint4 or libagx_fill based of size and object
alignment for clear_sizes which are a power of two up to 16.
Reported fill rate for 256MB buffers on a M1 Ultra (G13D) in
gpu-ratemeter is 355 GB/s for 16 byte aligned buffers and 155 GB/s for
4 byte aligned buffers.
Signed-off-by: Janne Grunau <[email protected]>
(cherry picked from commit 5c2d62c03072570e3ea394161717c52901c25327)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
3397d399 by Janne Grunau at 2026-02-25T14:22:21+01:00
hk: Use aligned vector fill in hk_CmdFillBuffer if possible
30% faster with 16KB buffers, more than twice as fast with 8MB and
larger buffers.
(cherry picked from commit 651a321ee211c74fa543865721c07f1d9df03cf2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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47caf527 by Olivia Lee at 2026-02-25T14:22:21+01:00
hk: fix passthrough GS key invalidation
Just seeing that a passthrough GS was already bound is not sufficient to
know that it is a *matching* passthrough GS. If the application binds a
new VS that requires a different passthrough GS key than the previous
VS, then we need to bind a different passthrough GS.
Fixes: 5bc82848163 ("hk: add Vulkan driver for Apple GPUs")
Signed-off-by: Olivia Lee <[email protected]>
Reviewed-by: Mary Guillemard <[email protected]>
(cherry picked from commit e10f29399fb4c973b574df0d3649dfe3b2b7e4cf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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c4bb6528 by Natalie Vock at 2026-02-25T14:22:21+01:00
radv/rt: Only use ds_bvh_stack_rtn if the stack base is possible to encode
The hardware only provides 13 bits for encoding the stack base (in
dwords). That translates to the stack base being required to be below
8192 dwords, or 32kB. It's possible to exceed this - LDS is 64kB after
all. Add an explicit check to make sure we don't end up with offsets
that overflow the hw's address fields. This fixes Metro Exodus Enhanced
Edition, which was using ray queries in a 1024-thread sized workgroup,
resulting in exactly 64kB of LDS being required for the stack.
This check isn't required for RT pipelines as we always use 32 or 64
wide workgroups with no other LDS used, so it's impossible to reach this
stack base limit.
Cc: mesa-stable
(cherry picked from commit 59a397793ea204df8a2ecfd89c7b6d96412a7f6d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
641a3ea0 by Mike Blumenkrantz at 2026-02-25T14:22:21+01:00
zink: fix broken compiler assert
cc: mesa-stable
(cherry picked from commit 44f2c40830078b48563b3d9f90ed17564f31f57a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
6f88b07e by Natalie Vock at 2026-02-25T14:22:21+01:00
radv: Initialize nir_lower_io_to_scalar progress variable
The NIR_PASS macro only overwrites this when the pass actually makes
progress. If the pass doesn't make progress, the variable stays
uninitialized.
Clang correctly spots this and warns about it.
Cc: mesa-stable
(cherry picked from commit 47e4a68a838347e65a5d4bef421d7c44c6f98314)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
a3f87263 by Aitor Camacho at 2026-02-25T14:22:21+01:00
kk: Fill pipelineUUID
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit b350f059f51c0876ecbdf4db46c774dc89171378)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
9a63c204 by Aitor Camacho at 2026-02-25T14:22:21+01:00
kk: Fix shader uint32_t value serialization
We need to write with blob_write_uint32 if we are using blob_read_uint32
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit 15c0dd39fc216d8de667441febdb2f06b1c5f0be)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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024143cc by Aitor Camacho at 2026-02-25T14:22:21+01:00
kk: Correctly release pipeline handles at shader destroy
The condition to release Metal pipelines incorrectly checks which shader
stage we are destroying leading to leads when graphics pipelines had to
be released.
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit 622ebba4763b1cf4909d3630f0329a53a04b7923)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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6152bf1c by Aitor Camacho at 2026-02-25T14:22:21+01:00
kk: Fix compute pipeline cache
When deserializing the compute shader from a blob, we need to recreate the
pipeline because the blob may have been loaded from file and therefore the
reference to the Metal resource will be invalid.
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit 75f6f46c0f834ca1883ffe58a33c33f5e00e9833)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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358c8f25 by Aitor Camacho at 2026-02-25T14:22:22+01:00
kk: Move gfx pipeline data to the info struct within kk_shader
Makes it easier to serialize and add data specific to the gfx pipeline.
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit 99d8246d1c0db7bb2a87213add0138a39eca5e66)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
40cf87c3 by Aitor Camacho at 2026-02-25T14:22:22+01:00
kk: Fix graphics pipeline serialization
Bundles all graphics pipeline creation information required by Metal into
the vertex shader so we can later rebuild the pipeline. This allows us to
correctly create pipelines from caches that were loaded from files.
Signed-off-by: Aitor Camacho <[email protected]>
(cherry picked from commit cdbf7242f3e68ca326dd1175c50c0a961dd3fda6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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22c27bd3 by Yiwei Zhang at 2026-02-25T14:22:22+01:00
venus: sync protocol for strict aliasing compliance
See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=124148 for details.
Backport log: headers are generated from the protocol used by 26.0
branch with the strict aliasing fix
(cherry picked from commit 6411ee0c2d51281e2faa8caaf8d264074942a393)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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dea37352 by Frank Binns at 2026-02-25T14:22:22+01:00
pvr/ci: move some timing out tests from fails to skips
Some of these test cases where already in the skip list.
Signed-off-by: Frank Binns <[email protected]>
(cherry picked from commit 74fd985c6c805474dac306f7ef4a4864aaabc1d7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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e1ae6626 by Frank Binns at 2026-02-25T14:22:22+01:00
pvr: Fix alloc callbacks usage when freeing frame buffers
When creating frame buffers the alloc callbacks are used in the host
allocations, those same alloc callbacks need to be used when freeing
those allocations but are missing in some places causing the CTS to
report memory leaks in certain test cases.
Fixes: 146364ab9f1 ("pvr: add support for VK_KHR_dynamic_rendering")
fix:
dEQP-VK.api.object_management.alloc_callback_fail.framebuffer
dEQP-VK.api.object_management.single_alloc_callbacks.framebuffer
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit 05ef9f01a7cf411935ba664729ea487f6e0f4d0d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
d68b3091 by Ian Romanick at 2026-02-25T14:22:22+01:00
brw/cmod: Don't propagate from CMP to ADD if there is a write between
If either source of the CMP is modified before an appropriate ADD is
found, the ADD and the CMP will not have the same result.
shader-db:
Lunar Lake
total instructions in shared programs: 17098815 -> 17098818 (<.01%)
instructions in affected programs: 1187 -> 1190 (0.25%)
helped: 0 / HURT: 3
total cycles in shared programs: 876858960 -> 876858968 (<.01%)
cycles in affected programs: 6878 -> 6886 (0.12%)
helped: 0 / HURT: 1
Meteor Lake, DG2, Tiger Lake, Ice Lake, and Skylake had similar results. (Meteor Lake shown)
total instructions in shared programs: 20034973 -> 20034984 (<.01%)
instructions in affected programs: 4599 -> 4610 (0.24%)
helped: 0 / HURT: 11
total cycles in shared programs: 881033088 -> 881033108 (<.01%)
cycles in affected programs: 57872 -> 57892 (0.03%)
helped: 0 / HURT: 5
fossil-db:
All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 918873064 -> 918873269 (+0.00%)
CodeSize: 14747338416 -> 14747339360 (+0.00%); split: -0.00%, +0.00%
Cycle count: 104141836677 -> 104141840371 (+0.00%); split: -0.00%, +0.00%
Totals from 205 (0.01% of 2011421) affected shaders:
Instrs: 290415 -> 290620 (+0.07%)
CodeSize: 4280704 -> 4281648 (+0.02%); split: -0.01%, +0.03%
Cycle count: 18166526 -> 18170220 (+0.02%); split: -0.00%, +0.02%
Closes: #14874
Fixes: 020b0055e7a ("i965/fs: Propagate conditional modifiers from compares to adds")
Reviewed-by: Matt Turner <[email protected]>
Tested-by: Jordan Justen <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
(cherry picked from commit d1614cd6db619e215f1e964cb22f0f8ef968aaaf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
024c5de5 by Ian Romanick at 2026-02-25T14:22:22+01:00
elk/cmod: Don't propagate from CMP to possible Inf + (-Inf)
This is a backport of BRW e26270249b1c.
shader-db:
All Intel platforms had similar results. (Broadwell shown)
total instructions in shared programs: 18623918 -> 18624594 (<.01%)
instructions in affected programs: 125179 -> 125855 (0.54%)
helped: 0 / HURT: 139
total cycles in shared programs: 957073100 -> 957072484 (<.01%)
cycles in affected programs: 16534168 -> 16533552 (<.01%)
helped: 42 / HURT: 68
Fixes: 020b0055e7a ("i965/fs: Propagate conditional modifiers from compares to adds")
Reviewed-by: Matt Turner <[email protected]>
(cherry picked from commit bdbfe8de4d82eee77f10ba9fb0e8da351785b3cf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
bfeb230f by Ian Romanick at 2026-02-25T14:22:22+01:00
elk/cmod: Don't propagate from CMP to ADD if there is a write between
If either source of the CMP is modified before an appropriate ADD is
found, the ADD and the CMP will not have the same result.
No shader-db changes on any ELK platform. I suspect the problematic
cases only occur after scheduling has rearranged instructions. This is
likely the reason BRW didn't experience this problem until 09450faf.
Fixes: 020b0055e7a ("i965/fs: Propagate conditional modifiers from compares to adds")
Reviewed-by: Matt Turner <[email protected]>
(cherry picked from commit da1fd9786b42671001354c6db68eb9ae4df81dc7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
849cdbcf by Rhys Perry at 2026-02-25T14:22:22+01:00
aco: fix gfx6-8 store_scratch() with function calls
Might happen with radv_emulate_rt=true.
Fixes the_great_circle/a6079328b8df7712 with polaris10.
Signed-off-by: Rhys Perry <[email protected]>
Fixes: e006f68b11ad ("aco/isel: Don't add scratch offset as gfx8- soffset if no offsets exist")
Reviewed-by: Daniel Schürmann <[email protected]>
(cherry picked from commit 75722da9096d315fe414346f47c53d30fa774016)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
5fa6c15b by Lionel Landwerlin at 2026-02-25T14:22:22+01:00
anv: apply the same ccs disabling for Xe3 than Xe2
The new compression scheme introduced in Xe2 also applies to Xe3, so
we're liable for the same bugs.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 2418c91537 ("anv/drirc: disable Xe2 CCS drm modifiers for GTK engine")
Reviewed-by: Tapani Pälli <[email protected]>
(cherry picked from commit 4ac47f8dded346fb272e0e61977c6debaba616ec)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
6f75431e by Lionel Landwerlin at 2026-02-25T14:22:22+01:00
anv: disable ccs modifier reporting when ccs modifiers are disabled
Reporting the modifiers when we're going to disable it in the back
hits various asserts in anv_image.c
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 2418c91537 ("anv/drirc: disable Xe2 CCS drm modifiers for GTK engine")
Helps: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14853
Reviewed-by: Tapani Pälli <[email protected]>
(cherry picked from commit 4f38b5c888a34cd6b06c89dcd6d742ca335e0ec6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
54293d4f by Samuel Pitoiset at 2026-02-25T14:22:22+01:00
radv: fix potential corruption after FMASK decompression on GFX6-8
While reworking image resolves completely in RADV, I found a very weird
bug where the only fix was to emit caches immediately after
decompressing the source resolve image (after FMASK_DECOMPRESS).
I have been struggling this for few hours and figured that it was
something related to context rolls (ie. as long the context was rolled
out, emitting the flushes immediately was required).
It turns out this was a known hardware bug on GFX6 that was implemented
in PAL. Though PAL only applies on GFX6 but GFX7-8 are also affected
based on my testing. Note that RadeonSI flushes CB_META too.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 837078b8d55651a6fa3031d91de88b9c77862ea0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
71145cb8 by Natalie Vock at 2026-02-25T14:22:22+01:00
radv/nir: Correctly handle workgroup sizes not aligned to 32
Since the stride is always 32 dwords, we need to treat the workgroup
size as multiples of that value. Using MAX2() only works for cases where
the workgroup size is less than 32, which was hit by some CTS with 1x1
workgroups.
Cc: mesa-stable
(cherry picked from commit b08f9f192ce881078aae442d22ec626703b4c81d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
b7752ddb by José Roberto de Souza at 2026-02-25T14:22:22+01:00
intel/perf: Add HSW verx10 to intel_perf_query_result_write_mdapi()
HSW is verx10 75 and when we switched from ver to verx10 I forgot to add the case
75.
Reviewed-by: Lionel Landwerlin <[email protected]>
Fixes: a097a3d214ed ("intel/perf: Change mdapi switch cases from ver to verx")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14902
Signed-off-by: José Roberto de Souza <[email protected]>
(cherry picked from commit 48c685ee39f8a69abb42824105b3176fb3d07bc9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
61f09295 by Emma Anholt at 2026-02-25T14:22:22+01:00
ir3/ra: Fix DOUBLE_ONLY limit pressure computation.
As the comment says, we want to limit our pressure based on underlying HW
reg file size, not max it out to HW reg file size. This caused us to not
spill when we should when the HW reg size was bigger than the ISA reg file
size, leading to OOB writes in RA when it tried to allocate to the limit
pressure we spilled to.
Fixes segfaults in llama.cpp's test-backend-ops.
Fixes: e6e34883a9e7 ("ir3: Add wavesize control")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14846
(cherry picked from commit 0c6da326f8c91de95f926558978fe0239ab41185)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
897f5814 by Faith Ekstrand at 2026-02-25T14:22:22+01:00
pan/clear: Stop packing undefined bits in colors
The util code doesn't actually fill things with zeros so the high bits
are undefined. If we really want things replicated, we need to mask off
just the bits we care about.
Cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Eric R. Smith <[email protected]>
(cherry picked from commit 4d8551552ef04daa8774b9d8a250589be04753c7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
3a92074d by Faith Ekstrand at 2026-02-25T14:22:23+01:00
nir/gather_info: Add support for panfrost tile load/store intrinsics
Fixes: 6fc1030e4fe7 ("nir: Add some new panfrost fragment shader intrinsics")
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Eric R. Smith <[email protected]>
(cherry picked from commit 88ad8bc75d0bbb72cd0a8786b1030a5df3fa3c23)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
37191db3 by Faith Ekstrand at 2026-02-25T14:22:23+01:00
panvk: Create both Z/S descriptors, even for separate Z/S
The Vulkan spec says that aspects are ignored for Z/S attachments so we
shouldn't consider that as a factor when deciding whether or not to
create other aspect descriptors. This will be irrelevant in a couple of
commits but we need it for the backport anyway.
Cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Eric R. Smith <[email protected]>
(cherry picked from commit 19ad26a8de7834bb6beba92c9d8eb7842b08ca48)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
e29de286 by Faith Ekstrand at 2026-02-25T14:22:23+01:00
panvk/preload: Stop assuming 32 registers
cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Eric R. Smith <[email protected]>
(cherry picked from commit 3bb7d929f4de31acce36675ab93fbc1e0d46a814)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
262e7fea by Faith Ekstrand at 2026-02-25T14:22:23+01:00
panvk/jm: Refactor BeginRendering()
The old code was all out of order and made no sense. There's a reason
it made no sense. It was wrong. Cleaning this up fixes a solid 1/3 of
the remaining Bifrost CTS fails in CI.
Cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Eric R. Smith <[email protected]>
(cherry picked from commit 962d1f33e17cd639e69b4bd8caa21e904a6a1c46)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
a457021d by Faith Ekstrand at 2026-02-25T14:22:23+01:00
panvk: Also load output attachments with LOAD_OP_NONE+STORE_OP_NONE
We already had this for LOAD_OP_DONT_CARE but we also need it for
LOAD_OP_NONE.
Cc: mesa-stable
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Acked-by: Boris Brezillon <[email protected]>
Acked-by: Eric R. Smith <[email protected]>
(cherry picked from commit 44ff0c4707bd12b5b655dbe26d6a8ed61391ca2c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
befb9af1 by Tapani Pälli at 2026-02-25T14:22:23+01:00
util: bring back fix to avoid strict aliasing bugs in xxhash
This is commit b9e163fa67e that got lost in xxhash upgrade 070bf8986ce.
Fixes graphics artifacts seen in multiple workloads with Intel driver
when using clang compiler.
Fixes also CTS tests:
dEQP-GLES31.functional.geometry_shading.layered.fragment_layer_cubemap
dEQP-GLES31.functional.geometry_shading.layered.fragment_layer_3d
dEQP-GLES31.functional.geometry_shading.layered.fragment_layer_2d_array
dEQP-GLES31.functional.geometry_shading.layered.fragment_layer_2d_multisample_array
v2: pass arguments from meson.build instead of hardcoding
(Eric Engestrom)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14684
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14107
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13895
Fixes: 070bf8986ce ("util: Upgrade xxhash.h to v0.8.3")
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit d2351b3d04d23e04398de234df53515b5a1dda5f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
54550955 by Samuel Pitoiset at 2026-02-25T14:22:23+01:00
radv/meta: fix depth/stencil resolves with different regions
This is possible since VK_KHR_maintenance10.
This fixes new VKCTS coverage in
dEQP-VK.pipeline.*.multisample.m10_resolve.*.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit ab6147e8ef79e58b955876083ef71d665ae2d19b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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499a7456 by Mike Blumenkrantz at 2026-02-25T14:22:23+01:00
zink: only do pre-sync transfer barrier after a renderpass
this is otherwise pointless and (for swapchain images) broken
(because they may never have acquired an image)
discovered by @valentine
cc: mesa-stable
(cherry picked from commit d47ba92d4224c0218757c24414b40879b7219e24)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
a163dec3 by Robert Mader at 2026-02-25T14:22:23+01:00
lavapipe: enable dmabuf import for planar drm formats
Like e.g. NV12. This just requires some minor fixes around offset
handling.
(cherry picked from commit 0b6340fd94e0cc946111df5304adf349de1d8680)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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d7607b6a by Benjamin Otte at 2026-02-25T14:22:23+01:00
lavapipe: Fix features for nonsubsampled ycbcr formats
The Vulkan spec says about VkFormatFeatureFlagBits:
If a format does not incorporate chroma downsampling (it is
not a “422” or “420” format) but the implementation supports
sampler Y′CBCR conversion for this format, the implementation
must set VK_FORMAT_FEATURE_MIDPOINT_CHROMA_SAMPLES_BIT.
Fixes: af062126ae1f26b01cad1165a4e31dc40e141b6b
Signed-off-by: Benjamin Otte <[email protected]>
(cherry picked from commit 0b6dd167ac72892fa6d1c70f9903c62a29e625f7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
697fbadd by Rhys Perry at 2026-02-25T14:22:23+01:00
aco: reset all vgpr_used_by_vmem_ in resolve_all_gfx11
Signed-off-by: Rhys Perry <[email protected]>
Backport-to: 26.0
Reviewed-by: Daniel Schürmann <[email protected]>
(cherry picked from commit dfda890ae839d8f2dc2b48ab7ca7a0aeaa763f7d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
ba82a167 by Rhys Perry at 2026-02-25T14:22:23+01:00
aco: resolve hazards before calls
Signed-off-by: Rhys Perry <[email protected]>
Backport-to: 26.0
Reviewed-by: Daniel Schürmann <[email protected]>
(cherry picked from commit 613b4fe407e9cbd6d27f0ac8c28cc2c23c02f640)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
- - - - -
ac49313d by Danylo Piliaiev at 2026-02-25T14:22:23+01:00
ir3: Align TCS per-patch output to 64 bytes to prevent stale reads
Empirically, TCS outputs have to be aligned to 64 bytes,
otherwise stale data may be read in rare cases. The exact
reason is not clear, but tests and proprietary driver behavior
strongly point at the need for 64 byte alignment.
Fixes tesselation issues in at least "Conan Exiles" but likely in many
more cases.
CC: mesa-stable
Signed-off-by: Danylo Piliaiev <[email protected]>
(cherry picked from commit 47251b2e2dc2097d1530b3def064dd56d545482c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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9ad2e488 by Nick Hamilton at 2026-02-25T14:22:23+01:00
pvr: Fix incorrect subpass merging optimisation
The subpass merging optimisation check for when subpasses are using
tile buffers was in the incorrect location.
The current check is in a function called from two places but only
the first of these should have been doing the optimisation check.
This was incorrectly affecting the number of renders that subpass
merging could avoid.
Partial fix for:
dEQP-VK.renderpass.*.attachment_allocation.input_output.71
Fixes: 10b6a0d567e9 ("pvr: Add support for generating render pass hw setup data.")
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit 0640ac7e3bdf632eee4e4aa47da5445e5deb4af4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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fb1ba13c by Jarred Davies at 2026-02-25T14:22:23+01:00
pvr: Fix allocating the required scratch buffer space for tile buffers
When calculating the dwords per pixel the output registers should
always be taken into account in addition to the number of tile buffers.
Fixes incorrect scratch buffer space calculation when both output
registers and tile buffers are emitted by a render.
Partial fix for:
dEQP-VK.renderpass.*.attachment_allocation.input_output.71
Fixes: 3457f8083a65 ("pvr: Acquire scratch buffer on framebuffer creation.")
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit df445dc9b97ea04fb4b37fdc5b42901a416cc519)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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a965c71e by Nick Hamilton at 2026-02-25T14:22:23+01:00
pvr: Rename pvr_render_input_attachment
The struct will also be used for preserve attachments in the next
commit.
Backport-to: 26.0
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit e18670347a2c923163135829c08026cc84b40dff)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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022e34b5 by Nick Hamilton at 2026-02-25T14:22:23+01:00
pvr: Add missing support for preserve attachments
In subpasses preserve attachments are not used by the subpass but
their contents must be preserved throughout the subpass.
Add a list for the preserve attachments info specified by a subpass
and when determining a subpass attachments total uses check the
preserve attachments list and add it uses to the total.
Partial fix for:
dEQP-VK.renderpass.*.attachment_allocation.input_output.71
Backport-to: 26.0
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit 0e01b9ef2df78f8ae28d3504ae64fadb5298c411)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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5000c315 by Jarred Davies at 2026-02-25T14:22:23+01:00
pvr: Add missing support for tile buffers to SPM EOT programs
Configure the EOT setup for SPM EOT programs so that the generated
programs load the tile buffer into the output buffer before doing
the emit
Partial fix for:
dEQP-VK.renderpass.*.attachment_allocation.input_output.71
Backport-to: 26.0
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit d1f2ad17dd6c0b4493ec2557ff09094e9033cd63)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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23cd27b1 by Nick Hamilton at 2026-02-25T14:22:23+01:00
pvr: Update CI fails list after render pass fixes
Backport-to: 26.0
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit b87d995d32e2a2d832ab023e3d22bb9084933920)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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6edfd323 by Nick Hamilton at 2026-02-25T14:22:23+01:00
pvr: Add support for fragment pass through shader
On the Rogue architecture add support for using a fragment passthrough
shader when there is no fragment shader present in a graphics
pipeline but the sample mask is required.
fix:
dEQP-VK.pipeline.monolithic.empty_fs.masked_samples
Backport-to: 26.0
Signed-off-by: Nick Hamilton <[email protected]>
Co-authored-by: Simon Perretta <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
(cherry picked from commit 14508b4c9a2d79ebaa872a8155221f330d8e1e21)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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6d7f2e3f by Samuel Pitoiset at 2026-02-25T14:22:23+01:00
ac/nir: fix writemask for dual source blending on GFX11+
This should definitely be an OR operation if MRT0 and MRT1 don't write
the same channels. This also requires to set the writemask manually
because when it's 0 (in case a dual-source output is missing), the
intrinsic computes the mask itself with the number of components.
No fossils-db changes on NAVI33.
Fixes: 45d8cd037a8 ("ac/nir: rewrite ac_nir_lower_ps epilog to fix dual src blending with mono PS")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/14878
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 2eb9420061334230afbd45861b8d40860f1e4ec1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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87a238d8 by Samuel Pitoiset at 2026-02-25T14:22:23+01:00
radv: fix potential GPU hangs with secondaries on transfer queue
Cache flushes should be skipped on SDMA. In practice,
radv_emit_cache_flush() should only be called on GFX/ACE.
SDMA NOP packets are emitted in barriers directly.
This fixes recent VKCTS coverage
dEQP-VK.api.command_buffers.secondary_on_transfer_queue.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit c4d5090d698f6e75dc317ad9226aadb09b498cb9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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77f3279c by Lionel Landwerlin at 2026-02-25T14:22:23+01:00
anv: dirty descriptors after blorp operations
Blorp emits 3DSTATE_BINDING_TABLE_POINTER_* instructions in 3D mode.
At the moment we're saved by the push constants reemitting the btp but
we'll drop that in the next commit.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit 533c748b34445a07a8e5b49d5a2c40ffca79c147)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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03847a6f by Lionel Landwerlin at 2026-02-25T14:22:23+01:00
anv: remove snprintf for aux op transition
With perfetto that string is processed later leading to
use-after-free.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit 413e169f453a6288f69880fd2ab4f0b7335089c4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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977f0409 by Mary Guillemard at 2026-02-25T14:22:24+01:00
hk: Fix crash in hk_handle_passthrough_gs
We should be returning if no GS is needed and no GS shader is bound.
This fix various segfaults introduced by the original fix.
Signed-off-by: Mary Guillemard <[email protected]>
Fixes: e10f29399fb4 ("hk: fix passthrough GS key invalidation")
Reviewed-by: Eric Engestrom <[email protected]>
Reviewed-by: Janne Grunau <[email protected]>
(cherry picked from commit 6d040df750fbf76b2d7cb22c95ec16e70ea04d0a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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f1a2f841 by Leon Perianu at 2026-02-25T14:22:24+01:00
pvr: fix format table properties duplicate
- RGBA8888_* is a preprocessor alias for R8G8B8A8_* in u_format.yaml.
- Both entries in the format tables collide on the same enum value, and
RGBA8888 overwrites R8G8B8A8.
- The fix was reverting to the version that was in the commit
39e949434c962150eb0fbca94e0618355098268a because there is a different format
was used that did not cause any collisions.
dEQP fixes:
dEQP-VK.api.info.format_properties.r8g8b8a8_sint
dEQP-VK.api.info.format_properties.r8g8b8a8_snorm
dEQP-VK.api.info.format_properties.r8g8b8a8_uint
dEQP-VK.api.info.format_properties.r8g8b8a8_unorm
Fixes: 9f740b26a61 ("pvr: Fix bugs in the format table")
Signed-off-by: Leon Perianu <[email protected]>
Tested-by: Icenowy Zheng <[email protected]>
Reviewed-by: Erik Faye-Lund <[email protected]>
(cherry picked from commit 7c6dbb099a58f4812aac9941fe55ffc881c95daf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40092>
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ed6f9676 by Eric Engestrom at 2026-02-25T16:54:23+01:00
docs: add release notes for 26.0.1
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bf5998be by Eric Engestrom at 2026-02-25T16:54:24+01:00
VERSION: bump for 26.0.1
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1acbba34 by Timo Aaltonen at 2026-02-26T21:56:17+02:00
control: Drop versions from mesa-va/vdpau-drivers Breaks/Replaces.
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8b145f81 by Timo Aaltonen at 2026-02-26T21:56:22+02:00
Merge branch 'upstream-unstable' into debian-unstable
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2eab6dd4 by Timo Aaltonen at 2026-02-26T21:56:30+02:00
New upstream release. (Closes: #1129015)
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a541e7ab by Timo Aaltonen at 2026-02-27T13:46:33+02:00
control: Add mesa-vdpau-drivers to mesa-libgallium Provides.
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d56d93c2 by Timo Aaltonen at 2026-02-27T13:48:14+02:00
releasing package mesa version 26.0.1-1
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e2c5233f by Christopher Obbard at 2026-02-27T13:50:41+02:00
Add Lintian override for Teflon delegate plugin location
libteflon.so is installed under /usr/lib/teflon/ as a TensorFlow Lite
delegate plugin. Delegates are loaded via dlopen() using an
application-provided absolute path and the C delegate ABI is
intentionally unversioned. Therefore this is not a "normal" shared
library meant to live in the multiarch libdir.
Add a Lintian override for arch-dependent-file-not-in-arch-specific-directory
for the Teflon delegate plugin library.
Signed-off-by: Christopher Obbard <[email protected]>
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130 changed files:
- .pick_status.json
- VERSION
- bin/gen_release_notes.py
- bin/pick/core.py
- bin/pick/core_test.py
- debian/changelog
- debian/control
- debian/control.in
- + debian/mesa-teflon-delegate.lintian-overrides
- debian/rules
- docs/relnotes.rst
- docs/relnotes/26.0.0.rst
- + docs/relnotes/26.0.1.rst
- docs/submittingpatches.rst
- meson.build
- src/amd/common/ac_cmdbuf_sdma.c
- src/amd/common/ac_cmdbuf_sdma.h
- src/amd/common/nir/ac_nir_lower_ps_late.c
- src/amd/compiler/aco_insert_NOPs.cpp
- src/amd/compiler/instruction_selection/aco_select_nir_intrinsics.cpp
- src/amd/vulkan/meta/radv_meta_fast_clear.c
- src/amd/vulkan/meta/radv_meta_resolve_cs.c
- src/amd/vulkan/meta/radv_meta_resolve_fs.c
- src/amd/vulkan/nir/radv_meta_nir.c
- src/amd/vulkan/nir/radv_nir_lower_ray_queries.c
- src/amd/vulkan/radv_cmd_buffer.c
- src/amd/vulkan/radv_pipeline_graphics.c
- src/amd/vulkan/radv_sdma.c
- src/amd/vulkan/radv_sdma.h
- src/asahi/vulkan/hk_cmd_draw.c
- src/asahi/vulkan/hk_cmd_meta.c
- src/compiler/nir/nir_clone.c
- src/compiler/nir/nir_functions.c
- src/compiler/nir/nir_gather_info.c
- src/compiler/spirv/spirv_to_nir.c
- src/freedreno/common/freedreno_devices.py
- src/freedreno/ir3/ir3_nir_lower_tess.c
- src/freedreno/ir3/ir3_ra.c
- src/gallium/drivers/asahi/agx_blit.c
- src/gallium/drivers/asahi/agx_pipe.c
- src/gallium/drivers/r300/ci/r300-rs740-fails.txt
- src/gallium/drivers/r300/ci/r300-rs740-flakes.txt
- src/gallium/drivers/r300/ci/r300-rv410-fails.txt
- src/gallium/drivers/r300/ci/r300-rv410-flakes.txt
- src/gallium/drivers/r300/ci/r300-rv530-nohiz-fails.txt
- src/gallium/drivers/r300/ci/r300-rv530-nohiz-flakes.txt
- src/gallium/drivers/r300/r300_texture_desc.c
- src/gallium/drivers/radeonsi/si_pipe.c
- src/gallium/drivers/zink/ci/zink-lavapipe-validation-settings.txt
- src/gallium/drivers/zink/ci/zink-tu-a618-fails.txt
- src/gallium/drivers/zink/ci/zink-tu-a618-validation-settings.txt
- src/gallium/drivers/zink/zink_compiler.c
- src/gallium/drivers/zink/zink_context.c
- src/gallium/frontends/lavapipe/lvp_device.c
- src/gallium/frontends/lavapipe/lvp_formats.c
- src/gallium/frontends/lavapipe/lvp_image.c
- src/imagination/ci/bxs-4-64-fails.txt
- src/imagination/ci/bxs-4-64-skips.txt
- src/imagination/vulkan/pvr_arch_cmd_buffer.c
- src/imagination/vulkan/pvr_arch_device.c
- src/imagination/vulkan/pvr_arch_formats.c
- src/imagination/vulkan/pvr_arch_framebuffer.c
- src/imagination/vulkan/pvr_arch_hw_pass.c
- src/imagination/vulkan/pvr_arch_pass.c
- src/imagination/vulkan/pvr_arch_pipeline.c
- src/imagination/vulkan/pvr_arch_spm.c
- src/imagination/vulkan/pvr_device.c
- src/imagination/vulkan/pvr_framebuffer.h
- src/imagination/vulkan/pvr_pass.h
- src/imagination/vulkan/pvr_pipeline.h
- src/imagination/vulkan/pvr_usc.c
- src/imagination/vulkan/pvr_usc.h
- src/intel/compiler/brw/brw_from_nir.cpp
- src/intel/compiler/brw/brw_nir.c
- src/intel/compiler/brw/brw_nir_rt.c
- src/intel/compiler/brw/brw_opt_cmod_propagation.cpp
- src/intel/compiler/brw/brw_opt_cse.cpp
- src/intel/compiler/brw/test_opt_cmod_propagation.cpp
- src/intel/compiler/elk/elk_fs_cmod_propagation.cpp
- src/intel/compiler/elk/elk_fs_cse.cpp
- src/intel/compiler/elk/elk_nir.c
- src/intel/isl/isl_surface_state.c
- src/intel/perf/intel_perf_mdapi.c
- src/intel/vulkan/anv_batch_chain.c
- src/intel/vulkan/anv_formats.c
- src/intel/vulkan/anv_image.c
- src/intel/vulkan/genX_blorp_exec.c
- src/intel/vulkan/genX_cmd_buffer.c
- src/kosmickrisp/vulkan/kk_physical_device.c
- src/kosmickrisp/vulkan/kk_shader.c
- src/kosmickrisp/vulkan/kk_shader.h
- src/mesa/program/prog_parameter.c
- src/mesa/program/prog_parameter.h
- src/mesa/state_tracker/st_format.c
- src/mesa/state_tracker/st_glsl_to_nir.cpp
- src/panfrost/ci/panfrost-g52-fails.txt
- src/panfrost/ci/panfrost-g925-fails.txt
- src/panfrost/genxml/v13.xml
- src/panfrost/lib/pan_clear.c
- src/panfrost/vulkan/csf/panvk_vX_cmd_draw.c
- src/panfrost/vulkan/jm/panvk_vX_cmd_draw.c
- src/panfrost/vulkan/panvk_vX_cmd_desc_state.c
- src/panfrost/vulkan/panvk_vX_cmd_draw.c
- src/panfrost/vulkan/panvk_vX_cmd_fb_preload.c
- src/panfrost/vulkan/panvk_vX_image_view.c
- src/util/00-mesa-defaults.conf
- src/util/meson.build
- src/virtio/venus-protocol/vn_protocol_driver.h
- src/virtio/venus-protocol/vn_protocol_driver_buffer.h
- src/virtio/venus-protocol/vn_protocol_driver_buffer_view.h
- src/virtio/venus-protocol/vn_protocol_driver_command_buffer.h
- src/virtio/venus-protocol/vn_protocol_driver_descriptor_pool.h
- src/virtio/venus-protocol/vn_protocol_driver_descriptor_set.h
- src/virtio/venus-protocol/vn_protocol_driver_descriptor_set_layout.h
- src/virtio/venus-protocol/vn_protocol_driver_device.h
- src/virtio/venus-protocol/vn_protocol_driver_device_memory.h
- src/virtio/venus-protocol/vn_protocol_driver_fence.h
- src/virtio/venus-protocol/vn_protocol_driver_framebuffer.h
- src/virtio/venus-protocol/vn_protocol_driver_image.h
- src/virtio/venus-protocol/vn_protocol_driver_image_view.h
- src/virtio/venus-protocol/vn_protocol_driver_pipeline.h
- src/virtio/venus-protocol/vn_protocol_driver_queue.h
- src/virtio/venus-protocol/vn_protocol_driver_render_pass.h
- src/virtio/venus-protocol/vn_protocol_driver_sampler.h
- src/virtio/venus-protocol/vn_protocol_driver_semaphore.h
- src/virtio/venus-protocol/vn_protocol_driver_structs.h
- src/virtio/venus-protocol/vn_protocol_driver_transport.h
- src/virtio/vulkan/vn_device.c
- src/vulkan/runtime/vk_cmd_enqueue.c
- src/vulkan/wsi/wsi_common_metal.c
The diff was not included because it is too large.
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/d31f29be870947e3ff95a80f583c27bdccb28ba6...e2c5233fc5188dcf3a7798b059bc457d2c4aac43
--
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/d31f29be870947e3ff95a80f583c27bdccb28ba6...e2c5233fc5188dcf3a7798b059bc457d2c4aac43
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