[Git][xorg-team/lib/mesa][debian-unstable] 223 commits: docs: add sha sum for 26.1.2
"Timo Aaltonen (@tjaalton)" <[email protected]> Thu, 02 Jul 2026 07:10:55 +0000
| Newsgroups | gmane.linux.debian.devel.x |
|---|---|
| Message-ID | <[email protected]> |
Timo Aaltonen pushed to branch debian-unstable at X Strike Force / lib / mesa
Commits:
c653d150 by Eric Engestrom at 2026-06-03T11:45:28+02:00
docs: add sha sum for 26.1.2
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f195147f by Eric Engestrom at 2026-06-17T12:45:49+02:00
.pick_status.json: Update to 11c903246655184d12fcead8888486c5ae796eef
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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2d95953f by Eric Engestrom at 2026-06-17T12:45:49+02:00
.pick_status.json: Mark 62b90b082916433dd137642ab11f174be14d4c15 as denominated
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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7996ef29 by Nick Hamilton at 2026-06-17T12:45:49+02:00
pvr: Fix load-op shader when loading from a 2d image view of a 3d image
When zink translates glCopySubImageData with a 2d image view of a 3d
image as the destination to a draw call the shader generated for the
load-op was not handling things correctly leading to the wrong
z-slice been loaded.
The fix is to mark which attachments within the load op are 2d image
views of a 3d image then when generating the load-op shader covert
the sample to 3d sample and update the coords to load the required
z-slice value from the tex meta data.
Fix for dEQP-GLES31.functional.copy_image.non_compressed.*_to_texture3d
Fixes: 7b28b6c43d5 ("pvr, pco: implement VK_EXT_image_2d_view_of_3d")
Signed-off-by: Nick Hamilton <[email protected]>
Reviewed-by: Luigi Santivetti <[email protected]>
(cherry picked from commit 46853bff6396e6091aa4957975bcae94d7be0dae)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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d761b338 by gyeyoung at 2026-06-17T12:45:49+02:00
panvk: fix flags2-only bit leak in legacy format features
VkFormatProperties uses VkFormatFeatureFlags, whose valid bits are limited to
VK_ALL_FORMAT_FEATURE_FLAG_BITS (0x7fffffffu).
Without this mask, the last bit leaks out.
Use vk_format_features2_to_features() helper when filling VkFormatProperties so
flags2-only bits are not leaked through legacy feature fields.
Cc: mesa-stable
Signed-off-by: Gyeyoung Baek <[email protected]>
Reviewed-by: Christoph Pillmayer <[email protected]>
(cherry picked from commit ff6e4fc335f7a997ae68a795ba38cc3b4511a6df)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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25f2bf4d by gyeyoung at 2026-06-17T12:45:49+02:00
panvk: report DRM format modifiers through List2EXT
panvk previously reported DRM format modifiers only through
VkDrmFormatModifierPropertiesListEXT.
Report them through VkDrmFormatModifierPropertiesList2EXT as well.
Cc: mesa-stable
Signed-off-by: Gyeyoung Baek <[email protected]>
Reviewed-by: Christoph Pillmayer <[email protected]>
(cherry picked from commit 65596f7053c8e5d840708153468047005dc22db0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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d9f99c00 by Mike Blumenkrantz at 2026-06-17T12:45:49+02:00
zink/clear: fix full_clear condition in texture clear
cc: mesa-stable
(cherry picked from commit 6accf9a5767cf141324d6cea918389b8e4e29d8c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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a824c45c by Mike Blumenkrantz at 2026-06-17T12:45:49+02:00
zink/clear: handle texture clears on current fb texture
need to ensure existing clears are flushed before applying these
cc: mesa-stable
(cherry picked from commit 01cbcdfe2ee777ae6e6f5c1ab04b64ed6b1c666a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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b93e2feb by Ashley Smith at 2026-06-17T12:45:49+02:00
panfrost: Fix tiler_desc assignment
Bifrost/valhall descriptor pointers are incorrectly assigned
Reviewed-by: Lars-Ivar Hesselberg Simonsen <[email protected]>
Reviewed-by: Daniel Stone <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Fixes: 11fcb23f74c ("pan/desc: Add a struct for valhall/bifrost to the union in pan_tiler_context")
Signed-off-by: Ashley Smith <[email protected]>
(cherry picked from commit fea2af1b7ba546de4fc5e92fa6ef6386a55f2f45)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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79a77908 by Ryan Zhang at 2026-06-17T12:45:49+02:00
gfxstream/platform: add missing inc_include to platform_virtgpu build
src/gfxstream/guest/platform/VirtGpu.cpp
| In file included from ../sources/mesa-26.0.6.imx/src/util/os_misc.h:42,
| from ../sources/mesa-26.0.6.imx/src/gfxstream/guest/platform/VirtGpu.cpp:12:
| ../sources/mesa-26.0.6.imx/src/util/u_math.h:42:10: fatal error: c99_compat.h: No such file or directory
| 42 | #include "c99_compat.h"
| | ^~~~~~~~~~~~~~
| compilation terminated.
Fixes: 5826a0a ("gfxstream: meson format -i {all meson files}")
Signed-off-by: Ryan Zhang <[email protected]>
(cherry picked from commit 072041a8098229d129d107f8618d8e95ebc9c430)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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f9d0a3af by Christian Gmeiner at 2026-06-17T12:45:50+02:00
mesa: Allow GL_TEXTURE_IMMUTABLE_LEVELS query on GLES3
GL_TEXTURE_IMMUTABLE_LEVELS is core state in OpenGL ES 3.0 (it comes with
immutable textures / glTexStorage), queryable through glGetTexParameter. The
getter only allowed it when ARB_texture_view or OES_texture_view is present, so
a GLES3 driver without texture views returns GL_INVALID_ENUM for a valid query.
Its sibling GL_TEXTURE_IMMUTABLE_FORMAT is correctly ungated.
Allow the query on any GLES3 context, matching the spec.
Fixes 8 dEQP-GLES3.functional.state_query.texture.*_immutable_levels_* cases on
etnaviv (which exposes neither texture-view extension).
Fixes: 214fd4e40db ("mesa/main: fix texture view enum checks")
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Adam Jackson <[email protected]>
Reviewed-by: Erik Faye-Lund <[email protected]>
(cherry picked from commit 75a0cd6e2cdcb32b0ff12be42175c0c4ba286459)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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0fb18b9f by Eric Engestrom at 2026-06-17T12:45:50+02:00
.pick_status.json: Mark fdb9ce608758bd63ff9cde151b31612f38cb3c84 as denominated
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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500b527f by Georg Lehmann at 2026-06-17T12:45:50+02:00
nir: preserve infinities and signed zero during atan2
For zero inputs, we end up with intermediate infinities from
frcp(0.0). The final output is not infinity though, so this has to
be well defined even when applications don't request preserving infinities
on their own. Also preserve signed zeros to make the sign of the infinities
well defined.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15585
Cc: mesa-stable
Tested-by: Tapani Pälli <[email protected]>
Acked-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit 3a815a596935c2ec9ba218829861d948ce2a17d1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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853d899f by Karol Herbst at 2026-06-17T12:45:50+02:00
vtn/opencl: convert libclc workaround handling to a switch statement
Cc: mesa-stable
(cherry picked from commit 3531a05fdd90498f84f805317422f7cb84841544)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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ba62f764 by Karol Herbst at 2026-06-17T12:45:50+02:00
vtn/opencl: fix edge case behavior for cospi
Cc: mesa-stable
(cherry picked from commit 8c109381ed82eb87a89d0d70225676736271b9c1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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e26ed821 by Karol Herbst at 2026-06-17T12:45:50+02:00
vtn/opencl: fix edge case behavior for sinpi
Cc: mesa-stable
(cherry picked from commit 1e9b1075b6ddd977508bd5b69465a8c0a73ec6eb)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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c6eff19d by Karol Herbst at 2026-06-17T12:45:50+02:00
vtn/opencl: fix edge case behavior for tanpi
Cc: mesa-stable
(cherry picked from commit a6172f19a0915fc690104a02e894b263d982e247)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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d9ab6962 by Pierre-Eric Pelloux-Prayer at 2026-06-17T12:45:50+02:00
radeonsi: fix sdma copy for gfx10
The shared sdma code used the "sdma_supports_compression" field from info
but radeonsi code still relied on gfx level checks.
Fixes: f5ecc5ffd5d ("ac,radv,radeonsi: add ac_emit_sdma_copy_tiled_sub_window()")
Reviewed-by: Marek Olšák <[email protected]>
(cherry picked from commit 3b3181a14d24c78fe7ebf18deabe6ed752dfc98a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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82742e8d by Mario Kleiner at 2026-06-17T12:45:50+02:00
wsi/display: Improve connector->last_nsec timestamping.
This improves reliability of VK_EXT_present_timing on wsi/display
and should be backported to Mesa 26.1-rc.
When latching connector->last_nsec timestamps from either a
drmCrtcGetSequence() query, or from a vblank sequence event
timestamp extracted as part of wsi_display_sequence_handler()
-> wsi_display_fence_event_handler() call sequence, the vblank
timestamps are in nanosecond precision/granularity, whereas
latched timestamps from a pageflip completion event in a call
to wsi_display_page_flip_handler2() are in increments of 1000
nsecs, based on microsecond precision/granularity timestamps.
All timestamp sources are based on the same DRM/KMS timestamps,
bit the different interfaces/api's expose those in different
precision.
This could cause a connector timestamp from the sequence path
in nanoseconds to be overwritten by a new timestamp from a
pageflip completion event that is truncated down to the next
lowest microsecond, causing time in connector->last_nsec to
go backwards by up to 999 nsecs. A MAX2 operator prevents
this.
Additionally, this also updates connector->last_nsec from a
successful Vulkan client call to vkGetSwapchainCounterEXT(),
allowing for a potentially more recent and thereby accurate
connector->last_nsec timestamp to be used as baseline for
scheduling timed FRR presents via VK_GOOGLE_display_timing or
VK_EXT_present_timing.
This is an improvement originally made by Keith Packard in his
original VK_GOOGLE_display_timing KHR_Display implementation,
just forward ported by myself, adding a slightly more descriptive
comment in the code.
See MR 38472 for reference of Emma's work, based on Keith's work.
The code from the original commit was...
Signed-off-by: Keith Packard <[email protected]>
Reviewed-and-tested-by: Mario Kleiner <[email protected]>
Fixes: 5e2814c8a475 ("wsi/display: Implement present timing on KHR_display.")
Cc: mesa-stable
Signed-off-by: Mario Kleiner <[email protected]>
Reviewed-by: Hans-Kristian Arntzen <[email protected]>
(cherry picked from commit f7fb4dd5ff5264737293231b758025b4291f1695)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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a7053949 by Mario Kleiner at 2026-06-17T12:45:50+02:00
wsi/display: Add workaround for all-zero valued pageflip events.
Both local testing and the Mesa CI's VK-CTS VK_GOOGLE_display_timing
test cases show some oddity of amdgpu-kms driven AMD gpu's wrt.
VK_EXT_present_timing and upcoming VK_GOOGLE_display_timing:
The very first present (atomic commit / pageflip) after a full
modeset commit which turns the associated output / connector from
fully off to on (powering up the display hw) will not send a
regular pageflip completion event, but instead send a pageflip
completion event after display hw programming is completed, with
all-zero vblank sequence count and present timestamp. This would
cause invalid timestamps for this very first present reported to
clients, and trips up the VK-CTS VK_GOOGLE_display_timing conformance
tests, because the first present is signalled as completed before it
was even queued. This failure can be observed with AMD gpu's in the
CI, but not with Intel or Qualcomm gpu CI, where CTS is successful.
Note this quirk doesn't happen for regular modesets on an already
running output, ie. one with at least one active hw plane. It does
happen for the CTS, as it seems to start from a powered off output.
Work around this AMD quirk:
1. Detect a pageflip event with all zero frame count and timestamp.
2. Try to query the count and timestamp of the most recent vblank,
as a likely good substitute for the "completed" pageflip, given
that pageflip and vblank counts and timestamps must always match
for the vblank of actual flip completion.
3. If the query should fail or also report non-sensical values, e.g.,
completed before queued, fall back to current system time as a
ok'ish result. Note that during my local testing on AMD Polaris11
with DCE-11.2 display engine this 3rd case was not ever observed,
and 2 did a good job. This is just a fallback for the fallback.
For reference, after digging through lots of amdgpu DC Linux source
code, the relevant decision code for deciding for a regular pageflip
event dispatched from the pageflip completion interrupt handler is
to be found by searching for the call site of the function
prepare_flip_isr(). The fallback code for the special "full modeset
to power on the display engine and skip regular pageflip event" is
the call site of the function drm_send_event_locked().
Successfully tested on AMD Polaris 11, DCE 11.2 display engine, and
also by Mesa CI's VK-CTS VK_GOOGLE_display_timing test cases for
direct display mode on AMD gpu's.
Signed-off-by: Mario Kleiner <[email protected]>
Fixes: 5e2814c8a475 ("wsi/display: Implement present timing on KHR_display.")
Reviewed-by: Hans-Kristian Arntzen <[email protected]>
(cherry picked from commit b4a1756fd1f37b28858ba4c871188c1bf2b6f4f3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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02fdb85a by Mario Kleiner at 2026-06-17T12:45:50+02:00
wsi/display: Deal with vblank-less systems for VK_EXT_present_timing.
Some hw + kms driver combos do not support vblank related functions
at all, ie. no drmCrtc[Get/Queue]Sequence() ioctl, no crtc sequence
events, no vblank of pageflip completion reported in pageflip events.
Most notable under the present_timing supported Vulkan drivers is
Asahi Linux on Apple Silicon Macs, with no such support: Only pageflip
events with a valid flip timestamp are supported.
To deal with this, we detect lack of vblank support and instead
use the current "vrr timing" path, which doesn't use vblanks, but
absolute time and timed waits. This also required a slight restructuring
of the setup logic.
Also fix semantics of requested relative timed presents via
VK_PRESENT_TIMING_INFO_PRESENT_AT_RELATIVE_TIME_BIT_EXT. The
spec states that the given target time should be relative to
the most recently presented image on a swapchain, and that if
no such image was presented yet (during the first present on
a swapchain), the relative target present time should be ignored.
Take care of this by tracking vblank count and time of the most
recent completed swapchain present separately from the most recent
known vblank count and time of the connector. Choose the swapchain
most recent present vblank data as baseline for relative timed
presents, to optimally implement spec semantics, but the connectors
vblank data for absolute timed presents to minimize rounding errors
and drift when converting between time and vblank cycle counts.
Signed-off-by: Mario Kleiner <[email protected]>
Fixes: 5e2814c8a475 ("wsi/display: Implement present timing on KHR_display.")
Reviewed-by: Hans-Kristian Arntzen <[email protected]>
(cherry picked from commit d7b23e9f3a95164429e4dbdb8e3b9d04572ce18f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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d6fa4199 by Mario Kleiner at 2026-06-17T12:45:50+02:00
wsi/common: Small compliance fixes for VK_EXT_present_timing.
- Queueing a present with VkPresentTimingsInfoEXT in the .pNext chain of
VkPresentInfoKHR, but VkPresentTimingsInfoEXT.pTimingInfos == NULL is
allowed and must not crash, just no-op.
- VkPresentTimingInfoEXT.targetTime == 0 means to ignore targetTime and
to simply present as soon as possible. This is achieved by setting
info->targetTime == 0 ==> target_time = 0. Make sure target_time stays
also 0 if targetTimeDomainPresentStage is set to
VK_PRESENT_STAGE_QUEUE_OPERATIONS_END_BIT_EXT, ie. skip the device->cpu
conversion via wsi_swapchain_present_convert_device_to_cpu(), as that
might map a zero info->targetTime device time to a non zero cpu
target_time.
Signed-off-by: Mario Kleiner <[email protected]>
Fixes: 47d69664d8f ("vulkan/wsi: Add common infrastructure for EXT_present_timing.")
Reviewed-by: Hans-Kristian Arntzen <[email protected]>
(cherry picked from commit 784a41cb8b855c3540d4479ac046dcc48a317652)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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6d205b2b by Mario Kleiner at 2026-06-17T12:45:50+02:00
wsi/common: Allow VK_EXT_present_timing present without presentStageQueries.
Spec allows to request a present at a specific target time or duration
without actually storing + querying any present records about completion
time. Iow. it allows VkPresentTimingInfoEXT.presentStageQueries == 0.
In this case, skip allocation and processing of a timing history record,
but still assign a VkPresentTimingInfoEXT.targetTime for timed present.
Signed-off-by: Mario Kleiner <[email protected]>
Fixes: 47d69664d8f ("vulkan/wsi: Add common infrastructure for EXT_present_timing.")
Reviewed-by: Hans-Kristian Arntzen <[email protected]>
(cherry picked from commit 2beb0c8820587b272b72ecac0ba3733bc5b392df)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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4e43858d by Samuel Pitoiset at 2026-06-17T12:45:50+02:00
radv/rt: fix a memory leak with hash tables
Found with ASAN.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit e247bdae0f912d3bc93c7768e03da78fe3ee550f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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4009692f by Samuel Pitoiset at 2026-06-17T12:45:50+02:00
radv/rt: fix a memory leak with the RT prolog NIR
radv_meta_nir_init_shader() allocates it and it must be freed.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 68273972d89697a41bbff7ba481520f4c498c4eb)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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8249c35d by Samuel Pitoiset at 2026-06-17T12:45:50+02:00
radv/rt: fix a memory leak with ahit/isec group
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit c9acff31fb04a49e5c982748b3181392f0b137a5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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02520422 by Samuel Pitoiset at 2026-06-17T12:45:50+02:00
radv: fix a memory leak with perfcounters
radv_physical_device::perfcounters must be freed.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit e622cbee6427f30e1bd33437124c4653398c106b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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e60bf294 by Daniel Stone at 2026-06-17T12:45:50+02:00
ci/panfrost: Switch T860 jobs to another RK3399 device type
The kevins are increasingly creaky and unreliable after a decade of
excellent service, so it's time to send them off to the farm and move
our T860 jobs to a device type which can actually run jobs.
Signed-off-by: Daniel Stone <[email protected]>
(cherry picked from commit 404a4f4d22b7666c672d41f04408c5c04a25402e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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58cf78e6 by Benjamin Cheng at 2026-06-17T12:45:50+02:00
draw: Add lower_opcodes NIR pass
Gallivm runs shaders that are originally compiled with another backend's
compiler options, which may have optimizations that introduce opcodes
that gallivm does not support. Add a pass to lower these.
Assisted-by: Claude Opus 4.6
Signed-off-by: Benjamin Cheng <[email protected]>
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit a4a862a6052391eabc78122bbd59b3934e1fa889)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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341223d3 by Benjamin Cheng at 2026-06-17T12:45:50+02:00
mesa/st: run the lower_opcodes pass for draw shaders
Fixes: 5eb0136a3c5 ("mesa/st: when creating draw shader variants, use the base nir and skip driver opts")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15304
Signed-off-by: Benjamin Cheng <[email protected]>
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit a989ca8c8f353484ccd79c4fb1c26b6f9aec66ea)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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2433f070 by Danylo Piliaiev at 2026-06-17T12:45:50+02:00
tu: Disable concurrent binning by default due to perf regressions
Unfortunately we have to disable concurrent binning by default
because it hurts performance in a number of desktop games without
any case where we know it helps.
There are less vertex fetch resource available in BV compared to BR,
so when binning runs in BV, there are many vertices, and vertices are
attribute heavy - BV has much worse performance than BR, sometimes more
than 50% worse.
Even with worse performance it won't be bad if concurrent binning
actually overlapped with other workload in those cases, but in case of
desktop games - there is almost never a chance for overlap.
However it's impossible to statically find out if binning on BV would
be much slower than on BR, and we also cannot statically predict if
there is enough overlap (if any) to cover for the performance penalty.
Given the above, I don't see a way out but to make concurrent binning
opt in via `tu_allow_concurrent_binning` driconf toggle.
Still allow concurrent binning in CI to catch issues early.
Signed-off-by: Danylo Piliaiev <[email protected]>
(cherry picked from commit 5529f15f31b0cd9c13f611148fcf9b272efd6b56)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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c39520b9 by Vinson Lee at 2026-06-17T12:45:50+02:00
ethosu/mlw_codec: silence warnings in the vendored Regor encoder
gcc reports two warnings in the weight encoder vendored from Arm's
Regor compiler (Ethos-U Vela):
src/gallium/drivers/ethosu/mlw_codec/source/mlw_encode.cpp:224:9:
warning: variable 'common_val' set but not used
[-Wunused-but-set-variable]
src/gallium/drivers/ethosu/mlw_codec/source/mlw_encode.cpp:426:33:
warning: comparison of integer expressions of different signedness:
'int' and 'long unsigned int' [-Wsign-compare]
These files are imported verbatim from upstream, so rather than patch
the vendored source (which would diverge from upstream and be lost on
the next re-import) silence the two known warnings at build-config
level via cpp_args on the mlw_codec static library. The suppression is
kept narrow so that any other warning introduced by a future re-vendor
still surfaces.
Fixes: d66d2c05d3f0 ("ethosu: Switch to the weight encoder from Regor")
Assisted-by: Claude Code (Claude Opus 4.8)
Signed-off-by: Vinson Lee <[email protected]>
(cherry picked from commit 25930dbc34f69450bae553c35d7c7c60b21ec3f2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
- - - - -
f2fd4b76 by Christian Gmeiner at 2026-06-17T12:45:50+02:00
etnaviv: Use integer texture formats for R32/RG32 integer textures
R32_SINT/UINT and R32G32_SINT/UINT are sampled as float, so a missing
channel is filled with a float default. A channel-expanding integer blit
then gets a float 1.0 alpha instead of integer 1, which fails 8 cases of
dEQP-GLES3.functional.fbo.blit.conversion such as rg32i_to_rgba8i.
The hardware support for integer texturing is unclear from RE and the
feature databases, so enable it on halti5 GPUs as a conservative
starting point.
Fixes: 64c7cdcae51 ("etnaviv: add missing formats")
Signed-off-by: Christian Gmeiner <[email protected]>
(cherry picked from commit b9c763454e6642dc90e47506d5b56f00c4b9b773)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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7b62ab7f by Vinson Lee at 2026-06-17T12:45:50+02:00
ethosu/mlw_codec: silence -Wunused-const-variable in vendored encoder
Compiling with clang produces a -Wunused-const-variable warning in the
weight codec vendored from Arm's Regor compiler:
src/gallium/drivers/ethosu/mlw_codec/source/mlw_decode.cpp:313:15:
warning: unused variable 'INITIAL_BLOCKS' [-Wunused-const-variable]
This warning is emitted only by clang, not by GCC, in the same vendored
mlw_codec sources whose other warnings are already suppressed at the
build-config level. Extend the existing cpp_args with
-Wno-unused-const-variable rather than patching the imported source, so
the files stay pristine for clean re-vendoring.
Fixes: d66d2c05d3f0 ("ethosu: Switch to the weight encoder from Regor")
Assisted-by: Claude Code (Claude Opus 4.8)
Signed-off-by: Vinson Lee <[email protected]>
(cherry picked from commit 3515c52e8cf31549b6068ef43c23c89830b6db46)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
- - - - -
4f318711 by Natalie Vock at 2026-06-17T12:45:50+02:00
radv/rt: Cache stack sizes of ahit/isec shaders from imported NIR
We need to save the stack size here separately, because the library
doesn't have the ahit/isec shader that uses stack.
Cc: mesa-stable
(cherry picked from commit 6a16319133d3d172f1c8fe5e213394ef831805e0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
- - - - -
673e7611 by Natalie Vock at 2026-06-17T12:45:50+02:00
radv/rt: Don't overwrite bvh_base at the start of the traversal loop
This may delete existing pointer flags coming from the instance if the
traversal loop is exited and then restarted, as is done with ray
queries.
Fixes geometry being incorrectly culled due to FLIP_FACING flags going
missing.
Cc: mesa-stable
(cherry picked from commit c8518581bf7b21ae114283cc49629d18e4cc1d2c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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50b1d19b by Mike Blumenkrantz at 2026-06-17T12:45:50+02:00
llvmpipe: create a zeroed payload for use without task shaders
this is never accessed, but spec requires that mesh shaders
can declare it (which implicitly accesses it because llvm branching)
fixes dEQP-VK.mesh_shader.ext.misc.payload_not_accessed
cc: mesa-stable
(cherry picked from commit 6094bed5a47f526a8bd3479e6d21ae4f6f53e0b5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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d54c04f9 by Yiwei Zhang at 2026-06-17T12:45:51+02:00
venus: fix unbound malloc leak in vn_ring_get_submits
Credits to Toshinari Morikawa, and this supersedes
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41904.
ring->free_submits can go unbound for heavy scenes that use 3 or more
shm pool allocs for CS storage. This change fixes to loop through the
free list for a cached entry, which is good enough in practice since
the most recently retired submit is cached at the list head.
Cc: mesa-stable
Reported-by: Toshinari Morikawa <[email protected]>
(cherry picked from commit 2cf1f6cb5088dcbe0523616169630e2e1f1de574)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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1ecb610e by Valentine Burley at 2026-06-17T12:45:51+02:00
tu: Fix vk_queue leak on submitqueue creation failure
tu_queue_init() calls vk_queue_init() before tu_drm_submitqueue_new().
If the DRM submitqueue creation fails, the function returns without
calling vk_queue_finish(), leaking the vk_queue resources.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit efe6f086c887857dca231052c26242493ba5ee65)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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81451d08 by Jose Maria Casanova Crespo at 2026-06-17T12:45:51+02:00
broadcom/compiler: fix payload-register liveness condition
vir_setup_def_use() pins a temp's live-interval start to ip 0 when it is
initialised from a payload register (W, centroid W, Z), which the hardware
sets up before the program runs. The range check is mis-coded with '||'
instead of '&&', so it matches every index and pins any QFILE_REG read,
not just payload reads.
On V3D 7.x the per-varying C coefficient lands in rf0 (QFILE_REG 0), so
every flat varying gets pinned live-from-start; a shader reading many
varyings then keeps them all live at once, inflating register pressure to
roughly the varying count and failing register allocation.
This fixes [email protected]@execution@varying-packing-mixed-types on rpi5
(previously crashing on RA failure).
Fixes: ce66c9aead9e ("broadcom/compiler: update payload registers handling when computing live intervals")
Assisted-by: Claude Opus 4.8
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit 116060607472be26eeed18412a6816e61b718399)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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ef4f9f38 by Timothy Arceri at 2026-06-17T12:45:51+02:00
nir: use the correct induction var when guessing loop iterations
Previously when loop analyze was guessing loop iterations based
on array/sample access, we incorrectly used the induction variable of
the loop terminator to calculate loop iterations, rather than
the induction variable that accesses the array/sample.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15550
Fixes: de30bfd5b845 ("nir/loop_analyze: ignore terminating induction variable in guess_loop_limit()")
Reviewed-by: Ian Romanick <[email protected]>
(cherry picked from commit 14a6aa3c15e797f1458b08658384b8438cbf25ca)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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138963d6 by yserrr at 2026-06-17T12:45:51+02:00
v3d: fix stencil blit layer selection
The stencil blit path used PIPE_TEXTURE_3D directly as a ternary
condition when computing the last layer. This tests the enum constant
itself rather than the resource target, so the 3D branch is always
selected.
Check src->base.target instead so non-3D stencil resources use their
array size when selecting the layer range.
Fixes: ac207acb97 ("broadcom/vc5: Implement stencil blits using RGBA.")
Signed-off-by: yserrr <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit 3bf366f349b02d702007c1cded7fc6908adcc7a0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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bf56140b by Tapani Pälli at 2026-06-17T12:45:51+02:00
iris: align down the max_shader_buffer_size
Fixes many failing CTS tests in following set:
KHR-Single-GL46.enhanced_layouts.ssb_member_invalid_offset*
See commit e58dcc47c3b that made the same change for radeonsi.
Fixes: 1eb4a2f5cd5 ("iris: Limit max_shader_buffer_size to INT32_MAX")
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit b33635bbe7ddcd8baf1bd1d442b4bc42c889766d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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ae57821c by Samuel Pitoiset at 2026-06-17T12:45:51+02:00
radv: add the mesh scratch ring BO to the preambles BO list
This was missing and this can technically causes issues.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 2b8b6fd292469fe26f9d864bee8ff6d544168f55)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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a99de84b by Mike Blumenkrantz at 2026-06-17T12:45:51+02:00
zink: always return DMA_BUF type handles from resource_get_handle
OPAQUE_FD here was a historical remnant (9fa7400564244bdd333066eb71285c3703b537f7)
from before zink actually handled dmabufs, but now that it does,
use dmabuf for exports since that's what is actually desired
cc: mesa-stable
(cherry picked from commit 824518737a25af7378b8afd8a5303d1893f12c67)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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c91b8168 by Paulo Zanoni at 2026-06-17T12:45:51+02:00
intel/blorp: fix blorp base key initialization
When you use designated initializers, anything that is not explicitly
set is set to zero. When you do something like:
struct blorp_blit_prog_key {
.base = BLORP_BASE_KEY_INIT(BLORP_SHADER_TYPE_BLIT),
.base.shader_pipeline = BLORP_SHADER_PIPELINE_RENDER,
};
the second initialization is the only one that does something: it sets
shader_pipeline to the desired value, and all the other fields in
"base" are set to 0. This is easily verifiable by just examining the
contents of all the blorp keys we initialize this way: name and
shader_type are always zero.
This means that if two blorp shaders of different types have the
same key size, the shader cache could confuse them. Still, I don't
think this is happening in the real world.
Fixes: 22ecb4a10f31 ("intel/blorp: Support compute for slow clears")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/11690
Reviewed-by: Ian Romanick <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
(cherry picked from commit 081dd1db75d863a6ef9fba884d3bb6f9a1f7a39d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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272368a6 by Calder Young at 2026-06-17T12:45:51+02:00
nir: Do not mask helper lanes of writes if ACCESS_INCLUDE_HELPERS is set
Fixes: 586da7b ("nir: Add nir_lower_helper_writes pass")
Reviewed-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 864bee8d4922607ac95721e716689f71a5f031c0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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4e722da3 by Tapani Pälli at 2026-06-17T12:45:51+02:00
anv: fix a null pointer access with isl_mod_info
It is possible for isl_mod_info to be NULL if no drm modifier was
given, layout transition on external queue can hit this condition.
Fixes: 11f8f333e23 ("anv: set a private binding when the image is not externally shared")
Signed-off-by: Tapani Pälli <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
(cherry picked from commit 93476c62994245aba4e3fef4acaaad90c91a61be)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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c33cf12b by Vinson Lee at 2026-06-17T12:45:51+02:00
radeonsi: remove duplicate '.bpp' initializer in si_sdma_copy_image
Compiling with clang produces a -Winitializer-overrides warning:
src/gallium/drivers/radeonsi/si_sdma_copy_image.c:217:17: warning:
initializer overrides prior initialization of this subobject
[-Winitializer-overrides]
The surf_src and surf_dst ac_sdma_surf initializers each set '.bpp = bpp'
twice: once next to the other scalar fields and once again after the
nested '.offset' initializer. The values are identical, so behavior is
unchanged, but the duplicate field initializer is redundant. Drop the
second one.
Fixes: e6e305988c76 ("ac,radv,radeonsi: merge tiled/linear surfaces into one struct")
Assisted-by: Claude Code (Claude Opus 4.8)
Signed-off-by: Vinson Lee <[email protected]>
Reviewed-by: Benjamin Cheng <[email protected]>
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 94c7ccbaa3540e384571c7438f48ca06cbac9cc6)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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520e396e by Lone_Wolf at 2026-06-17T12:45:51+02:00
clc: fix build with LLVM23 (TargetRegistry::lookupTarget)
See https://github.com/llvm/llvm-project/commit/d50631faad3003e73589528c83d3bbbad7ba72f1
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15471
Cc: mesa-stable
(cherry picked from commit f958ad11955638758c19170d9df4d67bf1ff8bcb)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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4c247072 by Georg Lehmann at 2026-06-17T12:45:51+02:00
radv/gfx12: program SPI_SHADER_PGM_RSRC4_GS for seperately compiled gs
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit a23fc3f066d6acf0f1efdf3116dfa0c6fda9e86b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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961e5a4e by Lionel Landwerlin at 2026-06-17T12:45:51+02:00
iris: only call brw_nir_fs_needs_null_rt() with no render targets
This helper was only meant to be called once the driver knows it
doesn't have any render target setup, to figure out whether an empty
one needs to be created.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Tested-by: Christoph Neuhauser <[email protected]>
Reviewed-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit d698cd7485f82400c5f4c41839d5e8dfeb9a9467)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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fc92e367 by Rhys Perry at 2026-06-17T12:45:51+02:00
ac/gpu_info: add has_smem_partial_oob_access_bug
Signed-off-by: Rhys Perry <[email protected]>
Backport-to: *
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit f7a388427882a7c75adefd18a3f30c8912fffb07)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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ccf3dc9c by Rhys Perry at 2026-06-17T12:45:51+02:00
radv: workaround has_smem_partial_oob_access_bug
Just use an existing flag to increase the bo size slightly.
Fixes a ring gfx timeout with
dEQP-VK.spirv_assembly.instruction.compute.opfma.fp32.vec3.undef.denorm_flush.directed
on vega10.
Signed-off-by: Rhys Perry <[email protected]>
Backport-to: *
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit addc719ec239f231ce1bcad2bc9b265798bd540a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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e67d9657 by Eric Engestrom at 2026-06-17T12:45:51+02:00
rusticl: skip bindgen for pipe_shader_state_from_tgsi
bindgen up to at least 0.72.1 generates invalid code (see below) and
that function is not used, so simply skip it.
src/gallium/frontends/rusticl/rusticl_mesa_bindings.c:795:81: error: duplicate ‘const’ declaration specifier [-Werror=duplicate-decl-specifier]
795 | void pipe_shader_state_from_tgsi__extern(struct pipe_shader_state *state, const const struct tgsi_token *tokens) { pipe_shader_state_from_tgsi(state, tokens); }
| ^~~~~
Backport-to: *
(cherry picked from commit 09ea05cf23fc6d116d18490569f13f010f790833)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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31532f92 by Eric Engestrom at 2026-06-17T12:45:51+02:00
meson: exclude known buggy versions of bindgen
Backport-to: *
(cherry picked from commit 47570e74ec81fc303a88b05aaf002703ea45e436)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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848b5786 by Michel Dänzer at 2026-06-17T12:45:51+02:00
egl/gbm: Ignore buffers with no BO for destroying excess BOs
Can't destroy a BO that doesn't exist in the first place.
Should fix the crash described in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41845#note_3510521 .
Fixes: dd7ae4109189 ("egl/gbm: Destroy excess BOs")
(cherry picked from commit 962fd789c82add4ec71e182ec9cd8f6245689d9c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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dcda10a6 by Michel Dänzer at 2026-06-17T12:45:51+02:00
egl/gbm: Ignore current front buffer in get_back_bo
Even if the front buffer isn't locked yet, it will normally get locked,
so we can't reuse it as a back buffer.
Pointed out by Daniel Stone.
Fixes: 4a976b60b113 ("egl_dri2: use gbm_surface as the native window type in drm platform")
(cherry picked from commit ab8e57cf3141ca7af0294c7f56aec85298e8bebf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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fede23fa by Danylo Piliaiev at 2026-06-17T12:45:51+02:00
tu: Add allow_oob_indirect_ubo_loads to device cache uuid
Fixes: f4c40fc89c7 ("tu: Add workaround for D3D11 games accessing UBO out of bounds")
Signed-off-by: Danylo Piliaiev <[email protected]>
Reviewed-by: Emma Anholt <[email protected]>
(cherry picked from commit fd99d813af9357d51698aa201adaa70e34064fa4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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f9ce79f6 by Job Noorman at 2026-06-17T12:45:51+02:00
ir3: fix possible signed overflow in ir3_link_add
`1 << 31` is undefined since `1` is a signed integer.
Signed-off-by: Job Noorman <[email protected]>
Fixes: 1f9839907a8 ("ir3: Skip missing VS outputs in VS out map when linking")
(cherry picked from commit 11334c438a48f63ee2b2fb63388fd52fc77d385a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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a5a4489a by Benjamin Cheng at 2026-06-17T12:45:51+02:00
radv/video: Set accurate minQp/QIndex
The spec requires us to follow the constantQp/base_q_idx from the app,
which is constrained by the caps. Report the more accurate caps.
Cc: mesa-stable
Signed-off-by: Benjamin Cheng <[email protected]>
Reviewed-by: David Rosca <[email protected]>
(cherry picked from commit b8b8035c6b40e84245ae2ce6849f34007c4c26af)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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1867024e by Benjamin Cheng at 2026-06-17T12:45:51+02:00
radv/video: Report MULTIPLE_SLICE_SEGMENTS_PER_TILE_BIT
VCN supports one tile only, but with multiple slice segments.
Cc: mesa-stable
Signed-off-by: Benjamin Cheng <[email protected]>
Reviewed-by: David Rosca <[email protected]>
(cherry picked from commit c2e76e111d4cb9e9fd435f7ab1ebb559434e6063)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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24922440 by Nanley Chery at 2026-06-17T12:45:52+02:00
anv: Set TRANSFER_DST_BIT for HiZ operations
VK_IMAGE_USAGE_TRANSFER_DST_BIT is needed to recognize a surface as a
destination in get_blorp_surf_for_anv_image(). Set this image usage for
HiZ operations to correct the MOCS programming on gfx12.0.
Fixes: 08e82b28e83 ("anv: use the correct MOCS for depth destinations")
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 28aba5fba48ce98a2bd6d1994ae457006343cd99)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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1fbd7a79 by nyanmisaka at 2026-06-17T12:45:52+02:00
intel/dev: update PTL device names
Ref: https://www.intel.com/content/www/us/en/products/sku/245531/intel-core-ultra-5-processor-338h-18m-cache-up-to-4-70-ghz/specifications.html
Ref: https://www.intel.com/content/www/us/en/products/sku/245523/intel-core-ultra-x7-processor-368h-18m-cache-up-to-5-00-ghz/specifications.html
Fixes: efa7aa4e ("intel/dev: Add PTL PCI IDs (with FORCE_PROBE set)")
Fixes: d84d7b78 ("intel/dev: Add PTL PCI IDs 0xb084-0xb087")
Signed-off-by: nyanmisaka <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
(cherry picked from commit 9dfa65db44c603fbb9ee07e3a0138c402c9ea8b8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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41556083 by Lionel Landwerlin at 2026-06-17T12:45:52+02:00
anv: fix assert/crash in import of compressed local memory on xe2+
There is no requirement that imported compressed memory is tied to an
image.
In practice it's unlikely to happen since unless drirc
anv_enable_buffer_comp is enabled we don't list the compressed memory
typed for anything but images. But you can build a case hitting the
assert without even creating an image.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 5a05a39e56 ("anv: Limit the SCANOUT flag to color images")
Fixes: b7f7f1c74f ("anv: Treat imported compressed buffers as displayable (xe2)")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15578
Reviewed-by: Tapani Pälli <[email protected]>
(cherry picked from commit 351c5d889cb3a7bca5740c2f9fcda51e2bdf44c1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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183a1e12 by Georg Lehmann at 2026-06-17T12:45:52+02:00
aco/ra: fix inline constants with v_dot2c_f32_f16
Unlike for v_pk_fmac_f16 and v_dual_dot2acc_f32_f16, opsel_hi is
implicitly true even for inline constants operands of v_dot2c_f32_f16 on GFX11.
Fixes: 3238e64d3ce ("aco/ra: create v_dot2c_f32_f16")
Reviewed-by: Rhys Perry <[email protected]>
(cherry picked from commit 3f2759af6c731dbbbdbaf7f2cb315e2fa701c705)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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8d31ad35 by Georg Lehmann at 2026-06-17T12:45:52+02:00
aco/sched_vopd: fix v_dual_dot2acc_f32_f16 created from VOP2 with inline constant
Fixes: 3238e64d3ce ("aco/ra: create v_dot2c_f32_f16")
Reviewed-by: Rhys Perry <[email protected]>
(cherry picked from commit 6cb9aaa2b7853f6299cfe674a3e444b2f4ac8d78)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
- - - - -
c1788146 by Mary Guillemard at 2026-06-17T12:45:52+02:00
nvk/nvkmd: Do not merge bind operations across VA mappings
We were allowing a possible merge of operation across VA mappings.
This is not a valid usage and will cause a ENOSPC to be returned by the
kernel side.
This fixes Forza Horizon 6 device lost when trying to enter in-game or
benchmark mode with VK_EXT_descriptor_heap MR.
Signed-off-by: Mary Guillemard <[email protected]>
Fixes: 053b7f0f30c ("nvk/nvkmd: Implement nvkmd_ctx for nouveau")
Reviewed-by: Mel Henning <[email protected]>
(cherry picked from commit b3f7f40b13d540314da5807ff82826c0c8ea764e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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6e441800 by Caio Oliveira at 2026-06-17T12:45:52+02:00
util: Fix float8 denorm rounding to min-normal
When rounding the largest FP8 denorm up, the code ignored the updated
exponent and returned zero instead of the minimum normal value. Pack
the updated exponent in those cases.
Fixes: 2237c022a20 ("util: add float8 conversion functions")
Assisted-by: Pi coding agent (GPT-5.5)
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit b941dd736ffc1ea4768954ab79886445dcef5473)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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314295ea by Juan A. Suarez Romero at 2026-06-17T12:45:52+02:00
Revert "people: update Marek's email"
This reverts commit b5063953caac18d90ca6fff67445599c9b39b2c3.
Marek is signing with his GMail account.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
(cherry picked from commit 25f698d6de37f67cd889f5973a42ae1f7d708e96)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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90b5eacf by Jakob Sinclair at 2026-06-17T12:45:52+02:00
pan/compiler: fix spilling for 64-bit values
For the BIR-compiler, 64-bit values were not properly tracked in the
spill logic and PHIs were always assumed to be 32-bits. This could
create issues were only one half of the value was reloaded or spills
would overlap each other leading to garbage values. This patch fixes
these issues by keeping track of how many words each value needs. Also,
it adds a constraint for SHADD sources where it splits and collects them
right before the SHADD instruction itself to make it easier for RA to
handle the register pairs.
Fixes: 4542982062a ("pan/compiler: Use SHADDX instruction for i64 add")
Reviewed-by: Christoph Pillmayer <[email protected]>
(cherry picked from commit 7606854f43972c780f03cbd851080edbf75114ec)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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94a62742 by Matt Turner at 2026-06-17T12:45:52+02:00
util, llvmpipe: flush subnormals to zero on ARM/AArch64
NEON always flushes subnormals to zero; previously lp_test_arit
special-cased vector paths to suppress the resulting failures.
The proper fix mirrors x86: set FPSCR/FPCR FZ so VFP also flushes,
keeping scalar and vector paths consistent with the C reference.
util_fpstate_{get,set,set_denorms_to_zero} now read/write FPSCR
(ARMv7) or FPCR (AArch64) via inline asm. flush_denorm_to_zero
in lp_test_arit flushes subnormal inputs on ARM/AArch64 to match.
Cc: mesa-stable
(cherry picked from commit 44c03f8ba65b023ae3297ba0f20ab3a8a62561b4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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cf417ac6 by Georg Lehmann at 2026-06-17T12:45:52+02:00
radv: fix setting inline push constants when only the last one is used
The 64bit mask was truncated, and then when the low half is 0, the base was -1.
By accident, u_bit_consecutive64(-1, 65) is the original mask, so we uploaded a
single garbage value.
Fixes: 7f6262bb85c ("radv: allow holes in inline push constants")
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit aacdaffc5ea86c345340fa7d932c4d5beeffce30)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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330f154d by Valentine Burley at 2026-06-17T12:45:52+02:00
anv/ci: Disable anv-adl-vk job
We already have VK CTS coverage on TGL and RPL, with the latter running
the full test suite pre-merge.
Having three gfx12 VK CTS jobs is redundant, so disable anv-adl-vk. The
ADL runners will be reused for a different job.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit 6f867bd3177f76efdba4a0a7b64a1146af74fa55)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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077cd3ba by Valentine Burley at 2026-06-17T12:45:52+02:00
venus/ci: Move pre-merge ANV coverage from Comet Lake to Alder Lake
Swap the pre-merge CML Venus-on-ANV job with the nightly ADL one, making
the ADL job pre-merge. Also Move the nightly Android CTS job to ADL.
The ADL runners are available after disabling anv-adl-vk, and this keeps
Venus-on-ANV coverage in Cuttlefish Android VMs.
Using 4 parallel runners allows the pre-merge VK CTS test suite to run
with a lower fraction. Update the xfails to match, since the new fraction
covers a different subset of tests.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit 057ff58fe6f455d06066ddea65082c3b2c3b9e77)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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5aff2dcd by Valentine Burley at 2026-06-17T12:45:52+02:00
venus/ci: Retire Intel Comet Lake runner
The Flip-hatch devices are getting retired in the Collabora lab.
We can also drop a few skips that were only needed for CML.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit 24d707d7e2ba16f90eb65c721a92d360dbcb9011)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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f28da3ca by Valentine Burley at 2026-06-17T12:45:52+02:00
venus/ci: Revert ADL jobs to stable 6.17 kernel
Xe is unstable on 6.18+, so we need to revert to the previous stable
kernel if we want to have pre-merge jobs on ADL.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit 51325d9ac3af007027a7f404c87f95dc19942bee)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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57a3294e by Lionel Landwerlin at 2026-06-17T12:45:52+02:00
anv: align storage texel buffer support on image support
We've enable image support based on typed write without format
support. Let's do the same for texel buffers.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/12384
Reviewed-by: Sagar Ghuge <[email protected]>
(cherry picked from commit 4e2abd872a1ff1c470f33f21a76adfeece754e93)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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f40b6b04 by Lucas Fryzek at 2026-06-17T12:45:52+02:00
Modify x11_xcb_display_supports_xshm to get xshm opcode
Previously this helper function would not capture the xshm opcode from
the server's shm reply and drisw_glx requires the value to work
properly.
Fixes: 5f4eccf1 ("glx: Check that xshm can be attached")
Reviewed-by: Eric Engestrom <[email protected]>
(cherry picked from commit db4159c431ac3160f21379c55c7c528efae316ab)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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52f765be by Marek Olšák at 2026-06-17T12:45:52+02:00
radv,radeonsi: disallow VRS flat shading if SubgroupInvocationID is used
The sysval is affected by VRS.
More subgroup sysvals might have to be added here.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]>
(cherry picked from commit 339945833c31bb2e2159d2b982cc3257818e305d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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e7e76536 by Radu Costas at 2026-06-17T12:45:52+02:00
pco: Set register classes for vec refs
Instructions that use a vec as a source were not having their subsequent
vtxin registers taken into account for reuse, just the 1st register in
the vec. Due to how vtxin regs function, reusing them while they are
still live can cause undefined behaviour. This change sets the registers
for all vtxin regs in the vec.
Fixes: 0ea39c63 ("pco: Use vertex input registers in register allocation")
Signed-off-by: Radu Costas <[email protected]>
Reviewed-by: Simon Perretta <[email protected]>
(cherry picked from commit 4942cd586ce5caaa2c6d7b0fd4257294b2c81830)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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69badf2d by Rhys Perry at 2026-06-17T12:45:52+02:00
radv/bvh: use atomic load/store in update_gfx12.comp
It looks like these are used to synchronize access to args.bounds, but
they were not atomic.
Signed-off-by: Rhys Perry <[email protected]>
Fixes: 2d48b2cb473 ("radv: Use subgroup OPs for BVH updates on GFX12")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15641
Reviewed-by: Georg Lehmann <[email protected]>
Reviewed-by: Konstantin Seurer <[email protected]>
Reviewed-by: Timur Kristóf <[email protected]>
(cherry picked from commit 4fe2ddf5e24fcee19ad072735ac6cfc250a3ed07)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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15e06f16 by Lionel Landwerlin at 2026-06-17T12:45:52+02:00
anv: add missing condition to update 3DSTATE_RASTER
update_clip_raster() checks the rasterization sample count.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Nanley Chery <[email protected]>
(cherry picked from commit 373ec78bc88c58f080bd52bc50cfd40728a750ef)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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a3813cb3 by Lionel Landwerlin at 2026-06-17T12:45:52+02:00
anv: fix 3DSTATE_SF line width programming with Bresenham lines
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Nanley Chery <[email protected]>
(cherry picked from commit 051ede709cb0447de25a8c749551d13ba6c45ac8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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32388423 by Caius-Moldovan-img at 2026-06-17T12:45:52+02:00
nir: Fix trailing comment generation for variable naming
Add semantic location check, because multiple variables can share same
component location.
Fixes: ea863c0c1cc ("nir/print: Do not access invalid indices of load_uniform")
Signed-off-by: Caius Moldovan <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
(cherry picked from commit 44290e189951581691b4ad6d0d3c209b6b806e14)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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d94ddbad by Samuel Pitoiset at 2026-06-17T12:45:52+02:00
radv: fix REPLAYED shader arena blocks not being marked as holes on free
Because free_list is always NULL for REPLAYED arenas, freed blocks were
never passed to add_hole() and freelist.prev was still NULL. So,
adjacent blocks were never merged together and that caused a memleak
with unreachable blocks.
This fixes a memleak detected by ASAN in
dEQP-VK.ray_tracing_pipeline.pipeline_library.configurations.singlethreaded_compilation.s0_l11_check_capture_replay_handles
and similar tests.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit d72d4666ba7625af731ee3decacc617db541c02e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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cbc6f453 by Samuel Pitoiset at 2026-06-17T12:45:52+02:00
radv/amdgpu: fix padding by one VM page
This isn't intended to be used for sparse BOs and it was incorrect
anyways because flags isn't initialized, so it was only clearing the
original VA range, not including the padding. Since sparse is still
experimental on GFX6-7, let's just apply the workaround to non-sparse
BOs.
This fixes sparse support on VEGA10, since addc719ec23
("radv: workaround has_smem_partial_oob_access_bug").
Fixes: 10a5e5e4f33 ("radv/amdgpu: Add ability to pad BOs with a read-only VM page")
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit ee5f5486789f0b3b05e17b869f5fca013adee2d5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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5491ed64 by Samuel Pitoiset at 2026-06-17T12:45:53+02:00
vulkan: fix lowering untyped accel struct with descriptor heap
It points to the heap variable.
This fixes
dEQP-VK.binding_model.descriptor_heap.basic.raygen.acceleration_structure_untyped.
Fixes: 20d11c59a44 ("vulkan: Add a lowering pass for descriptor heap mappings")
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 9a2d7186eb4cddf3fb6354e0b3d6e087e9622243)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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757d99a5 by Mike Blumenkrantz at 2026-06-17T15:18:42+02:00
zink: fix import2d sampler view creation
Fixes: cafa22142bf ("zink: create views for samplers lazily")
(cherry picked from commit e3903bc647281ab1b29f9d0c92e86b9b5d3ed4d9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42298>
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f2c772d4 by Eric Engestrom at 2026-06-18T08:44:14+02:00
docs: add release notes for 26.1.3
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6984e91b by Eric Engestrom at 2026-06-18T08:44:14+02:00
VERSION: bump for 26.1.3
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bfce4dd4 by Eric Engestrom at 2026-06-18T09:08:17+02:00
docs: add sha sum for 26.1.3
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62c038b1 by Timo Aaltonen at 2026-06-23T10:10:41+03:00
Merge branch 'upstream-unstable' into debian-unstable
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4f728f38 by Timo Aaltonen at 2026-06-23T10:13:17+03:00
version bump
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1a3d5de8 by Eric Engestrom at 2026-07-01T11:08:30+02:00
.pick_status.json: Update to a6bb4bbd1eaa8b1b8ba9e5df98ed2c9958393e40
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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99fefe4b by Eric Engestrom at 2026-07-01T11:08:30+02:00
gen_release_notes_test: don't evaluate backslash
Backport-to: *
(cherry picked from commit 30b3a19d61eaaa8534af42253a9df0db9c840eff)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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5f621a34 by Eric Engestrom at 2026-07-01T11:08:30+02:00
gen_release_notes: add support for "work_items" links
Caught-by: Georg Lehmann <[email protected]>
Backport-to: *
(cherry picked from commit 058e6c637b9ba7a32fa5cdb36d125d9480e3aaa1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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2667383c by Eric Engestrom at 2026-07-01T11:08:30+02:00
docs: fix release notes for 26.1.0
Due to the bug fixed in !42310, some fixed bugs were not tracked.
Fixes: 10f2c308c184960ec4f1 ("docs: add release notes for 26.1.0")
(cherry picked from commit 97a4815468a2a306306c3d9fe042062af381b6f7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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5579927c by Eric Engestrom at 2026-07-01T11:08:31+02:00
docs: fix release notes for 26.1.1
Due to the bug fixed in !42310, some fixed bugs were not tracked.
Fixes: 9b6d23e32b1cc30d23bd ("docs: add release notes for 26.1.1")
(cherry picked from commit 11c1c338e8e5c6ede6c63019eabe69397d3755b7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ad7bf870 by Eric Engestrom at 2026-07-01T11:08:31+02:00
docs: fix release notes for 26.1.2
Due to the bug fixed in !42310, some fixed bugs were not tracked.
Fixes: 0bad4fea86fa1ff7827c ("docs: add release notes for 26.1.2")
(cherry picked from commit e9c6c04fcb775d5d08ce6d1edb9bcc50d74a446f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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9642deba by Eric Engestrom at 2026-07-01T11:08:31+02:00
docs: fix release notes for 26.1.3
Due to the bug fixed in !42310, some fixed bugs were not tracked.
Fixes: f2c772d46382a2bdf8e4 ("docs: add release notes for 26.1.3")
(cherry picked from commit 3714a2a8dfd17042345cc09b72e3ea3aee111dbd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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e6ff2f03 by Daniel Schürmann at 2026-07-01T11:08:31+02:00
aco/assembler: Fix s_inst_prefetch insertion after loop latch rotation
If the loop latch is not the header, then the preheader ends in
a branch in order to jump over the loop latch on the first iteration.
Emit the s_inst_prefetch before the branch.
2415 (1.16% of 208626) affected shaders (Navi31)
Fixes: 102aca9843a69510b00f4807475cae3ee23931e4 ('aco/assembler: emit block_kind_loop_latch before the loop header')
(cherry picked from commit f43f2f7f7259a232213280fb9a542923e6916e6c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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d2bfbf9f by Georg Lehmann at 2026-07-01T11:08:31+02:00
aco/assembler: chain branches in emit order
Blocks aren't emitted in the order of program->blocks anymore,
use the real emitted order when chaining branches.
This fixes assumptions about block offsets only increasing.
Fixes: 102aca9843a ("aco/assembler: emit block_kind_loop_latch before the loop header")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15628
Reviewed-by: Daniel Schürmann <[email protected]>
(cherry picked from commit a3d9712e8e09024f094afd7b0efde2649f1ae2c9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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0c66d68c by Georg Lehmann at 2026-07-01T11:08:31+02:00
aco/assembler: don't reorder branch insertion block index twice
I hate everything about this code.
Fixes: a3d9712e8e0 ("aco/assembler: chain branches in emit order")
Reviewed-by: Daniel Schürmann <[email protected]>
(cherry picked from commit 1dc34d6dbafafbef973f82ccdad4c8c97e4a409f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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71c23ca2 by Rhys Perry at 2026-07-01T11:08:31+02:00
radv: fix barriers in decompress shaders
We used to not have nir_var_image, and nir_var_mem_ssbo was used instead.
Signed-off-by: Rhys Perry <[email protected]>
Backport-to: *
Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit 803e2c630354c14f9e3227a5805b120c46c6298d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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5815e9b7 by Boyuan Zhang at 2026-07-01T11:08:31+02:00
radeonsi/mm: use non-tmz buf when session tmz size is 0
If protected playback is enabled but session_tmz_size is zero,
no TMZ buffer is allocated and choosing session_tmz_buffer can
lead to a NULL dereference.
Update the selection logic to choose session_tmz_buffer only
when both protected is true and session_tmz_size is non-zero.
Otherwise, fall back to the regular session_buffer.
Cc: mesa-stable
Signed-off-by: Boyuan Zhang <[email protected]>
Reviewed-by: David Rosca <[email protected]>
(cherry picked from commit 02077584a6c1a0881e2812993c7e1047f31fa92d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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810f4f11 by Zeyang Lyu at 2026-07-01T11:08:31+02:00
radv: Add base array layer to htile offset
For gfx10_3, the base array layer needs to be included when calculating the HTILE offset.
Otherwise, copy_vrs_to_htile writes the VRS rate to an HTILE location different from the one used by depth/stencil.
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit a5a7acb6579b8d40537c85d5bde80effb0b59f3e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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7e6058ff by Zan Dobersek at 2026-07-01T11:08:31+02:00
fd: lrz_block in fdl6_lrz_layout_init() should not be static
Before in fdl6_lrz_layout_init() on a8xx, the lrz_block_sizes LUT and
lrz_block pointer were both declared as static. For the latter, this
meant that it was initialized based on the parameters of the first
invocation, and was then not properly assigned when subsequent
invocations were done for layouts with a different number of samples.
This led to incorrect LRZ layout calculation and subsequently incorrect
rendering on certain content.
The fix is simple, lrz_block should be declared separately and as
non-static. Finding the cause of the issue and the fix were done
independently, AI model was used to verify understanding of the
underlying cause.
Signed-off-by: Zan Dobersek <[email protected]>
Cc: mesa-stable
Fixes: 14a23e8b3e5 ("freedreno/lrz: Add gen8 lrz layout support")
Assisted-by: Claude Sonnet 4.6
(cherry picked from commit 6a010343d47b004cfd8ed859a8c35ebba0249a60)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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f6041eed by Marek Olšák at 2026-07-01T11:08:31+02:00
radv: fix setting COMPUTE_DISPATCH_INTERLEAVE on the gfx queue
it had undefined behavior because SET_SH_REG_INDEX(2) is required by this
register on the gfx queue
Cc: mesa-stable
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 66611c569f610372a14cd195268d1075ff22a0eb)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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875ed62e by Mary Guillemard at 2026-07-01T11:08:31+02:00
nvk: Default to output primitives as lines for tesselation parameters
With SET_TESS_PARAMS macro, we handle caching the previous parameters to
not reemit SET_TESSELLATION_PARAMETERS when possible.
However, we were wrongly setting up SET_TESSELLATION_PARAMETERS with
output_primitives=points during draw state initialization while the
default state of SCRATCH_TESS_PARAMS would map to
output_primitives=lines.
This adjust SET_TESSELLATION_PARAMETERS to the proper default value and
add a new MME test case for the default state to prove it.
This fixes tesselation tests failures on vkd3d-proton.
Signed-off-by: Mary Guillemard <[email protected]>
Fixes: 99bc2d9775e ("nvk: Merge tese/tesc state in the MME")
Reviewed-by: Mel Henning <[email protected]>
(cherry picked from commit b0046b8cb8f9d04bd69aac388304cfa92b68210b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
07db6fb9 by Lionel Landwerlin at 2026-07-01T11:08:31+02:00
brw: remove interpolator coarse bit setting
The return format with the coarse bit has a different format than the
non coarse variant, as described in ICL PRMs, Volume 9: Render Engine,
Coarse to Pixel Mapping Writeback Message (SIMD8 Message).
In particular register phases 0 & 1 are required, so we cannot use the
message with/without the bit interchangeably.
When making things more static (next commit) we get failures in tests
like :
dEQP-VK.pipeline.shader_object_linked_spirv.multisample_interpolation.offset_interpolate_at_pixel_center.137_191_1.samples_2
We probably never saw the issue because there is no test using the
interpolator with coarse pixel shading enabled and in most dynamic
cases the bit is not set so the return message has the expected
format.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 9b5774b11d679cf118c186e9b7768014dfa1fe9a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
43f92af2 by Georg Lehmann at 2026-07-01T11:08:31+02:00
aco/assembler: do not abort when exec is written after position exports
This can happen when the scheduler moves a reduce operation after the last
position export in legacy VS.
It also doesn't make sense to break here. In ancient aco history null exports
were added in the assembler just before the last exec write, but we no longer
do that.
Cc: mesa-stable
Reviewed-by: Rhys Perry <[email protected]>
(cherry picked from commit ae80aff95ab304405dd60d8123a2420b4d58109f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
9408bb83 by Marc Alcala Prieto at 2026-07-01T11:08:31+02:00
pan/va: Fix serialization of atomic operations using BI_ATOM_OPC_AUMIN
The UBO special case checked I->seg before checking the instruction
message, but atomics store I->atom_opc in the same union field. Since
BI_ATOM_OPC_AUMIN aliases BI_SEG_UBO, AUMIN atomics were skipped from
memory dependency tracking.
Only apply the UBO special case to load/store instructions so atomics are
serialized correctly.
Fixes test:
KHR-GLES31.core.shader_image_load_store.basic-allTargets-atomicCS.
Fixes: 41b39d6d5d8 ("pan/va: Do scoreboard analysis")
Reviewed-by: Christian Gmeiner <[email protected]>
(cherry picked from commit 4152da6d784cc6e649575e3fcd27ee77aa133616)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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879f0394 by Samuel Pitoiset at 2026-07-01T11:08:31+02:00
radv: fix a synchronization issue with taskmesh and pending cache flushes
The BOP event should be after pending cache flushes are emitted in the
GFX CS, otherwise the ACE CS might start too early and that could
cause some random synchronization issues.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 10911b5450a35c154f137b376e00f48ff4577866)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
8d3c7351 by Samuel Pitoiset at 2026-07-01T11:08:31+02:00
radv: fix a synchronization bug with DGC preprocess and taskmesh
If explicit DGC preprocess is used and emitted in a separate command
buffer, ACE must wait for the DGC prepare shader to be finished before
using it, otherwise it might just read invalid packets from the IB.
Because it's not possible to know if explicit DGC preprocess was
recorded in a separate cmdbuf, the only way to fix it is to make sure
that any compute dispatches are synchronized if task shaders are used.
This fixes random "Illegal opcode in command stream" issues
reported by AMDGPU with test_amplification_shader_execute_indirect_state
from vkd3d-proton.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 55b0d86af8e11e7aef68e389b5325a5cf5c8279c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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2408bd25 by Toshinari Morikawa at 2026-07-01T11:08:31+02:00
virgl: fix memory leak on shader translation
virgl_create_compute_state, virgl_shader_encoder was unnecessarily
cloning NIR. Since NIR is passed from st/mesa and the driver is
responsible for freeing it, virgl driver don't have to preserve
passed NIR and should free it through nir_to_tgsi_options.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13822
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Toshinari Morikawa <[email protected]>
(cherry picked from commit 0b1479eb6aa2b212c3bb02deadb64ad1b28a929e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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c422c6c4 by Job Noorman at 2026-07-01T11:08:31+02:00
ir3/opt_prefetch_descriptors: rematerialize defs at preamble start
When rematerializing defs in the preamble, we make sure to insert them
in a block dominated by all their sources. When inserting a def that
doesn't have any sources we have to make sure to insert them as early as
possible. This important for sequences like this:
32 %34 = load_const (0x00000007 = 0.000000)
...
if ... {
32 %184 = @load_preamble (base=8)
32 %185 = @bindless_resource_ir3 (%184) (desc_set=0)
32 %186 = @bindless_resource_ir3 (%34 (0x7)) (desc_set=1)
32x4 %187 = (float32)tex %186 (texture_handle), %185 (sampler_handle), ...
...
}
%185 has to be rematerialized in control flow since its source is
defined there. %186 does not as its source is defined outside control
flow. We used to insert %186 as late as possible
(nir_after_impl(preamble)) but this causes issues as we cannot find a
valid block (i.e., a block that is dominated by both) to insert the
descriptor prefetch for (%185, %186). Fix this by setting the default
block to insert rematerialized defs as the preamble's start block.
Totals from 520 (0.30% of 176258) affected shaders:
MaxWaves: 5796 -> 5794 (-0.03%)
Instrs: 715314 -> 715248 (-0.01%); split: -0.02%, +0.01%
CodeSize: 1547680 -> 1547182 (-0.03%); split: -0.17%, +0.14%
NOPs: 157057 -> 157005 (-0.03%); split: -0.07%, +0.04%
Full: 9399 -> 9415 (+0.17%)
(ss): 18718 -> 18715 (-0.02%); split: -0.03%, +0.01%
(sy): 8183 -> 8178 (-0.06%)
(ss)-stall: 79780 -> 79818 (+0.05%); split: -0.02%, +0.06%
(sy)-stall: 221660 -> 221591 (-0.03%); split: -0.05%, +0.02%
STPs: 232 -> 234 (+0.86%)
LDPs: 232 -> 234 (+0.86%)
Preamble Instrs: 242817 -> 242695 (-0.05%); split: -0.79%, +0.74%
Cat0: 176573 -> 176523 (-0.03%); split: -0.06%, +0.03%
Cat7: 18945 -> 18929 (-0.08%); split: -0.09%, +0.01%
Signed-off-by: Job Noorman <[email protected]>
Fixes: 4e2a0a5ad09 ("ir3: Add descriptor prefetching optimization on a7xx")
(cherry picked from commit 44b82c7576db6906987ccaf799a69dea28429cf0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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301ee9e0 by Christian Gmeiner at 2026-07-01T11:08:31+02:00
etnaviv: Flush texture caches after clears
A clear writes the surface through the BLT or RS engine while the
texture caches can still hold texels from an earlier draw that sampled
the cleared resource. Nothing invalidates them when the sampler view
stays bound, so the next draw samples stale data.
Clears of TS'd levels are not affected as sampling them goes through
the sampler TS or a resolve in etna_update_sampler_source(..), which
flushes the texture caches as a side effect.
Mark the texture caches dirty after clearing a samplable surface, like
etna_blit(..) and etna_transfer_unmap(..) already do.
Fixes dEQP-GLES3.functional.fbo.color.repeated_clear.sample.* with
ETNA_MESA_DEBUG=no_ts.
Cc: mesa-stable
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 695fec92f71ca8943890fc716cb28805931401d7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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49607bc8 by Christian Gmeiner at 2026-07-01T11:08:31+02:00
etnaviv: Add a helper for the 128-bit second-plane offset
The BA plane of an emulated 128-bit color level starts at
(size * depth) / 2. That offset is open-coded in the blt clear and the
transfer map/unmap paths, and the upcoming 128-bit render target and
sampler support adds more sites. Add
etna_resource_level_second_plane_offset(..) and use it, so the
invariant lives in one place.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit d5c507c6dbb81b18a0987883c3b7131961845861)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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9abf1c75 by Christian Gmeiner at 2026-07-01T11:08:31+02:00
etnaviv: Wrap pipe_framebuffer_state in etna_framebuffer_state
The 128-bit color emulation needs driver-private tracking next to the
framebuffer state. Introduce an etnaviv-private wrapper struct with
pipe_framebuffer_state as its base member. The tracking fields come
with the next commit.
All ctx->framebuffer_s.X accesses become ctx->framebuffer_s.base.X.
No behavior change.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 7d853e01b4e53242adafd36bdb669ed6d19a916f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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6be31c9e by Christian Gmeiner at 2026-07-01T11:08:31+02:00
etnaviv: Lay out 128-bit color FBO as paired G32R32F render targets
The PE cannot write 128-bit color formats (RGBA32F/UI/SI) natively. A
pair of 64-bit G32R32F render targets covers the same memory: the
user's RG channels go to RT[i] and the BA channels go to a companion
RT that points at the second plane of the same BO.
etna_set_framebuffer_state(..) appends one companion RT per 128-bit
user RT and records the mapping for the shader lowering and the
sampler side. The companion takes an extra resource reference so it is
released cleanly on unbind. The companion colormask is derived from
the user's blend state in etna_update_blend(..), the upper two bits
(B,A) move down to (R,G), so glColorMask works on both halves.
The per-RT restructuring drops the RT_CONFIG_UNK27 programming for
non-TS secondary RTs on CACHE128B256BPERLINE hardware. The bit must
not be set on the 128-bit companion RTs and its exact meaning needs
more reverse engineering. It can come back once understood.
Drawing still needs the NIR lowering from a later commit to split the
shader output into the RG and BA halves.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 7467461277cda032814d6f679c630d90c37b79ee)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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46727ea0 by Christian Gmeiner at 2026-07-01T11:08:31+02:00
etnaviv: Emit paired 128-bit sampler descriptors
Sampling a 128-bit color texture needs two G32R32F reads because the TE
knows nothing about the two-plane emulation. Emit a second sampler
descriptor at a companion slot that points at the BA plane. The shader
lowering later samples both slots and reassembles the vec4.
The BA descriptors reuse the descriptor slots of the RB_SWAP
native-order descriptors. The two cases cannot collide because no
128-bit format is RB_SWAP.
The companion of user slot i is the slot right after the bound views,
nr + i. A 128-bit view is only usable when nr + i fits the sampler pool,
asserted in debug builds. An out-of-pool companion stays at ~0U so the
emit path skips it and the shader lowering leaves the sample untouched,
the only fallout being wrong .ba data instead of a wild state write.
Dummy descriptors now cover every inactive dirty slot, not only the
previously-active ones, because a companion slot from an earlier bind
may never have been active.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit a49906787716d5f62dd1ae97179b2e298b5c0e90)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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e5bf0fd7 by Christian Gmeiner at 2026-07-01T11:08:32+02:00
etnaviv: NIR pass to lower 128-bit color RT and texture access
The hardware reads and writes the emulated 128-bit formats as two
G32R32F planes, so one store or sample in the shader has to become two.
Add etna_nir_lower_128bit to do that split at the NIR level, driven by
per-slot masks and companion tables in the shader key.
A store is split into an RG store to the user output and a BA store to a
companion output above the application visible range. A sample is cloned
to the companion sampler slot and the two results are reassembled into
the full vec4, with textureGather matching the blob's 16-bit halves. The
write mask is split alongside the data so partial writes keep their
meaning, and missing channels are padded with a typed zero so the
integer formats work.
set_sampler_views(..) computes the per-stage 128-bit mask once and the
per-draw shader key setup reads it back, so draws without 128-bit
textures only pay for a key compare.
Signed-off-by: Christian Gmeiner <[email protected]>
(cherry picked from commit 7436c8ad0bd26e5169ae5ff3047f757e082d1840)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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14b3b42b by Christian Gmeiner at 2026-07-01T11:08:32+02:00
etnaviv: blt: Use block-layout offset for 128-bit second-plane blit
The 128-bit emulation stores all RG halves in the first half of the BO
and all BA halves in the second half. The sampler descriptors, the CPU
upload and the BLT clear all compute the second plane as
(size * depth) / 2.
etna_try_blt_blit(..) advanced source and destination by layer_stride
instead, an interleaved layout nothing else uses. For single-layer 2D
targets both formulas coincide, so plain blits worked, but per-layer
blits of a multi-layer 128-bit array texture corrupted the BA half of
every layer. Use the same (size * depth) / 2 offset as the rest of the
emulation.
Fixes: 1f60a0397bb ("etnaviv: blt: Support 128 bit blit operations")
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 38eb315407103d64e119f978a4bedb824be20f49)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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9dbc220b by Christian Gmeiner at 2026-07-01T11:08:32+02:00
etnaviv: Save the framebuffer without 128-bit companion slots
etna_blit_save_state(..) saved the expanded framebuffer including the
appended companion slots. The util_blitter restore goes through
etna_set_framebuffer_state(..), which appends companions again, so every
blitter round trip with a 128-bit color buffer bound grew nr_cbufs until
the expansion assert fired.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 3d8a718181a386548e364d8625635de5fa46e451)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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9ed18803 by Christian Gmeiner at 2026-07-01T11:08:32+02:00
etnaviv: rs: Support 128-bit color clears
A 128-bit color level is laid out as two stacked G32R32F planes, so
clear it with two 64bpp RS fills, the RG half at the level offset and
the BA half at the second-plane offset.
A cache flush and stall separate the two fills. etna_clear_rs(..) needs
the same flush between its color and depth clears to avoid a GC600 hang,
and the blob brackets every RS operation this way. The blob clears
RGBA32F render targets through RS with the same plane split, verified
with a cmdstream capture on a faked GC7000 rev 6204 identity.
Fixes dEQP-GLES3.functional.fbo.color.repeated_clear.* for 128-bit
formats on RS-only halti5 hardware.
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit d75d08437beea7806fcd85221cd0e0fe0c773fa0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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a36784f6 by Christian Gmeiner at 2026-07-01T11:08:32+02:00
etnaviv: Limit nir_lower_fragcolor(..) to advertised render targets
nir_lower_fragcolor(..) expands a broadcast gl_FragColor into one store
per render target. It was passed specs->num_rts, the physical HW count,
but on HALTI2 only half of them are advertised (caps.max_render_targets)
since the upper half is reserved for float and 128-bit format emulation
companions.
A broadcast shader thus wrote into the reserved slots. For a 128-bit
target the clear meta shader stores to every gl_FragData and overwrote
the BA companion plane filled by etna_nir_lower_128bit(..), so the clear
came back with the RG half replicated into BA.
Pass the advertised count instead to keep the broadcast inside the user
visible range.
Fixes: 928a276b789b ("etnaviv: Limit max supported render targets")
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 9013b56a226ad88d626f13b2e594b41ce5369589)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ec9e40fa by Christian Gmeiner at 2026-07-01T11:08:32+02:00
etnaviv: Disable TS per render target on mixed TS modes
PE.MEM_CONFIG.COLOR_TS_MODE is a single global field, so every TS-enabled
color render target in a framebuffer has to share one TS mode. With
CACHE128B256BPERLINE the mode is picked per resource (256B for compressible
formats, 128B otherwise), so a compressible format bound next to an integer
format disagrees and the odd target gets decoded in the wrong mode, reading
back as the clear color.
The blob keeps TS on the targets that match the global mode and disables it
only on the odd one, instead of giving up TS for the whole framebuffer.
Compute a per-RT TS mask once in etna_set_framebuffer_state(..), store it in
etna_framebuffer_state and reuse it when arming the BLT fast clear, so the
two consumers stay consistent by construction. A disabled target keeps its
tile status allocated, so it recovers once a later framebuffer is compatible
again.
Fixes 23 dEQP-GLES3.functional.draw_buffers_indexed.random.* cases that mix
integer and unorm render targets, with no regression in fbo.color or fbo.blit.
Fixes: d70531ca931 ("etnaviv: Extend etna_update_ts_config(..) for MRTs")
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Daniel Lang <[email protected]>
(cherry picked from commit 37eb09ed06e583614377500b2b3692f66ee29f6c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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86f7d4c6 by Matt Turner at 2026-07-01T11:08:32+02:00
gallivm: fix lp_build_round on altivec/VSX
The software fallback in lp_build_round (used when
arch_rounding_available returns false, e.g. altivec with length < 4)
used lp_build_iround's bias-and-truncate path, which rounds
half-away-from-zero due to float32 rounding of the (a + nextafterf(0.5))
sum. This caused lp_test_arit failures for v1 and v2 vector widths on
ppc64.
For altivec/VSX, llvm.nearbyint lowers to vrfin (AltiVec) or xvrspic
(VSX) — both single instructions that round to nearest-even — for any
vector width. Use it in the else branch when has_altivec is set,
preserving the lp_build_iround path for x86 pre-SSE4.1 where
llvm.nearbyint would expand to scalar nearbyintf calls.
Update the length==2 expected-failure condition in lp_test_arit to
exclude altivec (now fixed), keeping it for other platforms that still
use the software fallback.
This fixes the lp_test_arit test on ppc64.
Cc: mesa-stable
(cherry picked from commit a9d70225eca226410a7455bbbb1eb6925b56b4b9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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a148d432 by Matt Turner at 2026-07-01T11:08:32+02:00
gallivm: fix small_unorm -> unorm8 fetch path on big-endian
Two bugs in lp_build_fetch_rgba_aos's small_unorm fast path:
- vector_justify=true shifted the loaded value into the MSB of the wider
type on big-endian. The format_desc already carries
big-endian-corrected channel shifts, so the extra shift broke channel
extraction for sub-32-bit formats (e.g. R8G8B8, B5G5R5).
- The output OR-loop packed channels assuming little-endian byte order
(shift = j * width), so after bitcast to vec4-u8 on big-endian the
alpha channel landed at byte[0] instead of byte[3].
The fix is simple: gather with vector_justify=false so format_desc
shifts apply directly; use (3-j)*width on UTIL_ARCH_BIG_ENDIAN to match
the memory layout that big-endian bitcast produces.
This fixes the lp_test_format test on big-endian platforms.
Cc: mesa-stable
(cherry picked from commit 5bb025f953af5795d2dc8fefc69ad22effb2a51b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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3214d684 by David Rosca at 2026-07-01T11:08:32+02:00
radeonsi/mm: Return error when decoding H264 P/B frame with no refs
The firmware expects at least one valid reference when decoding P and B
frames, otherwise it may pagefault.
If the app doesn't handle missing references by using dummy surfaces,
error out when trying to decode such frame.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15659
Fixes: 26979becec3 ("radeonsi/video: Add video decoder using ac_video_dec")
Reviewed-by: Benjamin Cheng <[email protected]>
(cherry picked from commit 61d2f8d0f1c6a9ad6a334bd94cbeffe70aa529c0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ba3e31c0 by David Rosca at 2026-07-01T11:08:32+02:00
radeonsi/mm: Only setup ref surfaces with tier3
For lower tiers this adds unnecessary dependency on the ref surface.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15630
Fixes: 26979becec3 ("radeonsi/video: Add video decoder using ac_video_dec")
Reviewed-by: Benjamin Cheng <[email protected]>
(cherry picked from commit 6cd7dd852a03ddade7ffbbd9e6c439402584276c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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db20b100 by David Rosca at 2026-07-01T11:08:32+02:00
radeonsi/mm: Set correct usage in si_dec_fill_surface
Fixes: 26979becec3 ("radeonsi/video: Add video decoder using ac_video_dec")
Reviewed-by: Benjamin Cheng <[email protected]>
(cherry picked from commit 08c2bb3b31db0eb9414ca0c8455c7a962797369c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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3014f0c7 by Juan A. Suarez Romero at 2026-07-01T11:08:32+02:00
v3dv: fix assertion on push constants
Fixes a compiler warning regarding the assertion.
Fixes: 6d6a3ab6793 ("v3dv: asserts push constants data is valid")
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit df96a100aef520f8b7745fe2e962cce06df0c15e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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3108615d by Mike Blumenkrantz at 2026-07-01T11:08:32+02:00
zink: when triggering zink_blit_barriers() for src==dst, apply separate barriers
combining the barriers prevents the write barrier from correctly clearing
the read flags, which breaks analysis for successive read barriers
cc: mesa-stable
(cherry picked from commit 206740815b40a8d0aab51a0f863a1ed631b28699)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
3138c3e4 by Yiwei Zhang at 2026-07-01T11:08:32+02:00
venus: amend roundtrip between fence submit and wait idle
The last virtgpu submission can end up with a tailing fence submit
racing with renderer side sync thread teardown during vkDestroyDevice.
This change ensures virtgpu side fence submits are done before the idle
wait fence submit via the ring.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15672
Cc: mesa-stable
(cherry picked from commit 8bc99ecb19e7145624364548e5f2b8e8462090b9)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
352cd24f by Adam Jackson at 2026-07-01T11:08:32+02:00
nvk: use unsigned comparison in UBO bounds checks
The pre Turing lowering path of load_global_constant_offset compared the
offset and size with ilt, but we need an unsigned check as offset can be
arbitrary and follows unsigned semantics.
When lowering non-uniform ldcx we also have to compare with ult for the
same reasons.
Assisted-by: Claude
Backport-to: *
Reviewed-by: Mel Henning <[email protected]>
(cherry picked from commit 055cee26b2db2ab0cead9c3b6d8b1fc4a3e267c2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
4bfcbc60 by Karol Herbst at 2026-07-01T11:08:32+02:00
nak: convert base to iadd for non-uniform ldcx lowering
The bound check only checked for the dynamic offset and ignored the
constant base one. This fixes the bound check, but also simulates 32-bit
overflow semantics due to the ldcx offset being 32 bits as well.
Backport-To: 26.1
Reviewed-by: Mel Henning <[email protected]>
(cherry picked from commit 304324eb288de91ab6440d95a2d2e54e3d6573ee)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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4c34c229 by Marek Olšák at 2026-07-01T11:08:32+02:00
nir: fix ibfe handling in ssa_def_bits_used
The outer condition is fixed to check correctly whether any sign-extended
bit is used.
The inner condition was supposed to check whether src2 is constant.
Fixes: 7d24a9b649be9125 - nir: handle ibfe/ubfe in nir_def_bits_used
Reviewed-by: Rhys Perry <[email protected]>
(cherry picked from commit ba8525aecca790f89b120d612a49df9554d4bf35)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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0872c7eb by Sam James at 2026-07-01T11:08:32+02:00
glx: append extra_ld_args_libgl, not clobber
We're adding an argument in a followup commit, so avoid clobbering it.
cc: mesa-stable
Signed-off-by: Sam James <[email protected]>
(cherry picked from commit 28bbf509c72634adfbca5b18614b0a1f3ff96938)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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032440c1 by Sam James at 2026-07-01T11:08:32+02:00
src: add -Wl,--no-fatal-rwx-sections for two libraries
If GNU Binutils is configured with --enable-error-rwx-segments=yes, the
linker will error out on RWX segments by default, which causes problems for
32-bit when -Dglx-read-only-text=false in:
* src/glx/libGLX_mesa.so
* src/gallium/targets/dri/libgallium.so
Pass -Wl,--no-fatal-rwx-sections if supported by the linker accordingly
for that case.
This is the same issue as mentioned in 39408229b50 ("ci: make linker warnings fatal").
cc: mesa-stable
Signed-off-by: Sam James <[email protected]>
(cherry picked from commit 7aea3e14dc6b3b85ccc5854e0f9156fc59cf3112)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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edc558b6 by Sam James at 2026-07-01T11:08:32+02:00
gallium/dri: fix redundant Meson condition
Since 4b54277d2e9, in this branch, with_gallium_va is always true. No
need to check it twice.
Fixes: 4b54277d2e9 ("Remove VDPAU")
Signed-off-by: Sam James <[email protected]>
(cherry picked from commit 4a6f6dd266cce89912d1eb093f141753626ef795)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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4b0e142a by David Rosca at 2026-07-01T11:08:32+02:00
vl: Skip transfer function and primaries conversion when not needed
cs_trc_apply clamps the value to 0 which causes issues in YUV->YUV conversions
that can have negative intermediate values after conversion to RGB.
If no transfer function and primaries conversion is needed, this step
can be skipped.
Fixes: 69717c257f8 ("vl,frontends/va: Implement gamma and primaries conversion")
Reviewed-by: Benjamin Cheng <[email protected]>
(cherry picked from commit f13f43904960082919d73b83a604a65ef3cabc16)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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cacbcc13 by David Rosca at 2026-07-01T11:08:32+02:00
va: Always reset compositor chroma location
Otherwise it would incorrectly use it for RGB formats if there
was a previous conversion with YUV formats.
Fixes: d0eec628310 ("frontends/va: Change vlVaPostProcCompositor to take pipe_vpp_desc arg")
Reviewed-by: Benjamin Cheng <[email protected]>
(cherry picked from commit 5d6e5a895fc71a9508143fd2d20850be1ef3cbd0)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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d2593c56 by David Rosca at 2026-07-01T11:08:32+02:00
va: Use RGB format with matching bit depth for YUV->YUV matrices
The bit depth used for the matrix calculation is derived from input
format.
Fixes: 5bc0df5aada ("vl,frontends/va: Implement YUV->YUV matrix coeff conversion")
Reviewed-by: Benjamin Cheng <[email protected]>
(cherry picked from commit 88baf64496d20e8c2a4994b0278b882c89e52ca8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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baee0976 by Valentine Burley at 2026-07-01T11:08:32+02:00
panfrost/ci: Move t860 jobs to nightly
The rk3399-gru-kevin devices are not reliable enough to host pre-merge
jobs, so move them to nightly.
Signed-off-by: Valentine Burley <[email protected]>
Acked-by: Erik Faye-Lund <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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b2c44867 by Juan A. Suarez Romero at 2026-07-01T11:08:32+02:00
broadcom/ci: fix kernel used on the baremetal rpi3 duts
Backport of only the baremetal part of that commit, to restore 26.1 CI.
Original commit below:
---
broadcom/ci: upgrade kernel in DuTs
Upgrade kernel to 6.18.34+rpt-rpi except for vc4/baremetal jobs
(pre-merge), as it doesn't load vc4 driver correctly.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
(cherry picked from commit 4781d59cfdb82d0705b2ec42f759a20adeefea1f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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28cce415 by Ahmed Hesham at 2026-07-01T11:08:32+02:00
nir: fix vectorising phis with mixed chased sources
nir_opt_vectorize compares phi sources using component 0
after chasing through movs. For multi-component phi sources, that first
component may not represent the whole source: it can be constant while
other components are not, or it can come from a different component range.
Reject multi-component phi sources unless all chased components are
constants, or come from the same def within the same max-vector component
range.
Fixes OpenCL-CTS test test_select.
Fixes: 6b611dbe ("nir/opt_vectorize: add support for phi nodes")
Signed-off-by: Ahmed Hesham <[email protected]>
Reviewed-by: Georg Lehmann <[email protected]>
Acked-by: Erik Faye-Lund <[email protected]>
(cherry picked from commit 3b5eecf990f1e47de927bd359ef46b16a9de33b2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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efe78f9b by Samuel Pitoiset at 2026-07-01T11:08:32+02:00
radv: workaround game bugs with Sniper Elite 5
For the Vulkan backend which contains many VVL errors.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 03ea3c1b504fe82b3f17fa70b043ccd717cde5ea)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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b6383252 by yserrr at 2026-07-01T11:08:33+02:00
v3d: remove duplicate util_blitter_save_so_targets() call
v3d_blitter_save() saves the stream output targets twice.
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit 38a98a48035aa25d6187fcd01eb69d28b0f98fbd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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a3d5c6d1 by Juan A. Suarez Romero at 2026-07-01T11:08:33+02:00
st/mesa: release sampler view
This fixes a leak.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Backport-to: 26.1
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit 5e093ccc80c45ee4a5fa5de03e7780401744c8c8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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19d1faa6 by Juan A. Suarez Romero at 2026-07-01T11:08:33+02:00
rusticl: fix leak in `util_queue`
As Box::into_raw() is called when adding a job, we need to call
Box::from_raw() so Rust recovers the track of the memory, avoiding a
leak.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Backport-to: 26.1
Reviewed-by: Karol Herbst <[email protected]>
(cherry picked from commit cfafa79447699ef4cb4e49cb5c584aefbce369ce)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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2334b752 by Juan A. Suarez Romero at 2026-07-01T11:08:33+02:00
v3d: free vertex and constant buffers on context destroy
This fixes several leaks found when running some piglit tests.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Backport-to: 26.1
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit b4d7bc7dc8fc938e36957218ae749f6ab8588ad8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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135f6757 by Juan A. Suarez Romero at 2026-07-01T11:08:33+02:00
v3d: add more blitter ops for saving resources
We were saving more resources than required, and this was generating
some leaks.
Add new operations so we only save resources that will be restored
later.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Backport-to: 26.1
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit a69aaadec1bd46b12a6cf4cb9e6c7e3789ef7a6b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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9c177c82 by Juan A. Suarez Romero at 2026-07-01T11:08:33+02:00
vc4: move util_copy_constant_buffer to the function beginning
Whether the constant buffer is NULL or not, we always want to copy it. Hence we do it as first step.
This fixes some leaks found when running piglit tests.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Backport-to: 26.1
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit 80a13eb5963a061dc906005dd7308bc31f9b7ab5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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472925a9 by Juan A. Suarez Romero at 2026-07-01T11:08:33+02:00
vc4: add blitter operations
So far we were saving all the resources before calling util_blitter. But
this is in charge of restoring later the resources, and it only restores
only those that were required to be saved before the blitter operation.
Which means we end up with multiple leaks.
We follow the same approach as other drivers, and only save the
resources that are affected by the blitter operation.
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Backport-to: 26.1
Reviewed-by: Iago Toral Quiroga <[email protected]>
(cherry picked from commit 99fab42da98777bb172656981790206978a05f74)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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833281c6 by Sam James at 2026-07-01T11:08:33+02:00
util: remove bogus const attribute
With GCC trunk (observed at r17-1670-g7374385c962b86), I saw a SIGFPE in
llvmpipe_init_compute_caps because lp_native_vector_width was 0.
This turns out to be because util_get_cpu_caps is marked with ATTRIBUTE_CONST
which imposes strong requirements [0].
In particular:
> The const attribute prohibits a function from reading objects that affect its
> return value between successive invocations.
[0] https://gcc.gnu.org/onlinedocs/gcc/Common-Attributes.html#index-const
Bug: https://gcc.gnu.org/PR125916
Fixes: 1b8a43a0baf ("util: Remove util_cpu_detect")
Signed-off-by: Sam James <[email protected]>
(cherry picked from commit 501433dff3dc46f1f3876dd32b6c1b731c7b2379)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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df5ee092 by Karol Herbst at 2026-07-01T11:08:33+02:00
nir/opt_phi_precision: bail on load_const conversions between float and ints
We should check the float constants for NaN and Inf while also trying to
avoid any other UB we might be running into here.
And because the weather is frying my brain, I'm just disabling the opt
when we deal with constants being of a different base type.
Fixes: c7b935962b2 ("nir: Add pass to lower phi precision")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15704
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit 512fe5b687ac41a58fcc3518f69dc1004db4d6f3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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7967736d by Karol Herbst at 2026-07-01T11:08:33+02:00
rusticl: move the worker queue into the Platform
We really don't want to spawn a bunch of threads for each new context,
especially if we start to make use of them internally (e.g. Meta).
Also wrap it around a LazyLock so we only initialize it when actually
used.
Backport-to: 26.1
Fixes: cfafa794476 ("rusticl: fix leak in `util_queue`")
Tested-by: Alyssa Rosenzweig <[email protected]>
(cherry picked from commit c4ae2d56eecfdbd043b39961e9f6c412b4d15384)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ea8be1d3 by Jeremy Huddleston at 2026-07-01T11:08:33+02:00
bin/install_megadrivers: Bail out if libname suffix is never reached
The symlink-stripping loops walk a versioned driver name down to its base suffix one extension
at a time. If the driver name doesn't contain the configured suffix at all, splitext eventually
returns an empty extension and the loop spins forever instead of making progress. Detect that
case and exit with failure so the install fails loudly rather than hanging.
CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15528
Fixes: ffd02b8ad84728d3529f1beeb06fb9212d31113b
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit c8f01b7648ec3f2c1ce497343401d00c67c17e8c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ad9e702a by Jeremy Huddleston at 2026-07-01T11:08:33+02:00
gallium/targets: Use libname_suffix for installed driver names
The dril and va driver lists hardcoded a .so suffix on every entry, and the dril build-tree
symlink target hardcoded libdril_dri.so. On macOS that mismatches the actual megadriver
(libdril_dri.dylib) and the --libname-suffix passed to install_megadrivers.py, which expects
the alias names to share that suffix. Build the driver name lists from bare basenames and
append libname_suffix at the consumption site so each platform installs with its native
shared-library suffix.
CC: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15528
Fixes: ffd02b8ad84728d3529f1beeb06fb9212d31113b
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 75581c5cd513480b4885335edc776295ecb238fd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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1b1fbc80 by Mike Blumenkrantz at 2026-07-01T11:08:33+02:00
tu: handle partially set resolve attachment info without crashing
setting only one of resolveMode or resolveImageView is legal and does not
initiate a resolve operation
cc: mesa-stable
(cherry picked from commit bc649a02d4c1ca2148ba6eb2e0a83fa774b4d037)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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19bec8e1 by Ryan Neph at 2026-07-01T11:08:33+02:00
anv/xe: prevent WaitIdle optimization for fences with exported sync_fd
Ensure sending non-empty execbuf to kmd for trivial queue submissions
containing an exported fence signaling op, so fence signal time is
accurate.
For Android systems built upon Angle-on-Vulkan this fixes Android CTS
test android.gpu.cts.EGL15Test#testEGL15AndroidNativeFence that asserts
the fence signal time is after fence create time.
Prior to this change, Xe kmd yields a stub fence via dma_fence_get_stub
with much earlier signal time.
Fixes: db5319fbf00 ("anv/xe: move special WaitIdle optimization to submission path")
Signed-off-by: Ryan Neph <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 114f3ff0cc032284c7f93712e8329b6ed50f393a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ee95e225 by Caio Oliveira at 2026-07-01T11:08:33+02:00
util: Add util_is_half_subnormal()
Reviewed-by: Ian Romanick <[email protected]>
(cherry picked from commit 554c9e5c82e36a3a56304277f406c2d15e1a0d4d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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24f49921 by Caio Oliveira at 2026-07-01T11:08:33+02:00
brw, elk: Fix invalid case using float-negation in combine constants
The negation of a floating-point value most of the time will correspond
to just flipping the sign bit. Combine constants do take advantage of
that together with the negate src modifier, so it can store less
constants in registers.
For example, when both 0x81111111 and 0x01111111 are used and in
conditions that neither can be used as immediate, combine constants is
able to store only one of them and the other is obtained with the negate
src modifier. For example if one value is in `r10.2` the other value
can be obtained by `-r10.2:f`.
There are cases where this transformation doesn't preserve the bits,
combine constants already accounted for NaN values, but missed subnormal
values.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15639
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15636
Fixes: 44d62a5224d0 ("intel/fs: Completely re-write the combine constants pass")
Reviewed-by: Ian Romanick <[email protected]>
(cherry picked from commit 5473f4b5e91280be98fa9dacac3b0f2da6eef7c7)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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e5001590 by David Rosca at 2026-07-01T11:08:33+02:00
radeonsi/mm: Fix setting VPE rotation when horizontal flip is enabled
0xF mask also includes PIPE_VIDEO_VPP_FLIP_HORIZONTAL.
Fixes: ed176e2c715 ("amd, radeonsi: add si_vpe.c with helper functions of VPE lib")
Reviewed-by: Peyton Lee <[email protected]>
(cherry picked from commit 485f06802aa5aa59ac3d6fe5f78dc44545f43151)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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007d0acb by Daniel Schürmann at 2026-07-01T11:08:33+02:00
aco/ra: Fix get_reg_impl() for operand registers
When used for Operands, the call to get_regs_for_copies()
could place other operands into the same registers.
Cc: mesa-stable
(cherry picked from commit b9f05ffe3bdf83f3e03a5c78a9807a02e735d668)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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000b3e42 by Yiwei Zhang at 2026-07-01T11:08:33+02:00
panvk: fix plane indexing for afbc image subres layout
The current path follows below mapping:
- 1 x panvk_image -> N x (1 x pan_image -> 1 x pan_image_plane)
Fixes: 11fe21d6591 ("panvk: change AFBC subresource layout pitches to byte sizes")
Reviewed-by: Boris Brezillon <[email protected]>
Reviewed-by: Marc Alcala Prieto <[email protected]>
Tested-by: Marc Alcala Prieto <[email protected]>
(cherry picked from commit 38994cb56e738a1533b2e4e94fb41ab3fd7014f2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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4a51daa4 by Paulo Zanoni at 2026-07-01T11:08:33+02:00
anv: don't put clear colors for aliased images in private bindings
According to the Vulkan spec:
"If two aliases are both images that were created with identical
creation parameters, both were created with the
VK_IMAGE_CREATE_ALIAS_BIT flag set, and both are bound identically
to memory except for
VkBindImageMemoryDeviceGroupInfo::pDeviceIndices and
VkBindImageMemoryDeviceGroupInfo::pSplitInstanceBindRegions, then
they interpret the contents of the memory in consistent ways, and
data written to one alias can be read by the other alias."
If we use private bindings for the clear colors, it could be that
VkImage A sets the clear color to red, VkImage B sets the clear color
to blue and clears it, then when A reads it, it should be blue, but it
will be red since its clear color is different.
On debug mode, before this patch we were hitting the first assertion
of check_memory_bindings():
assert(!aliased || from_wsi || video_decode ||
private_binding size is 0)
This could be reproduced, for example, in the Street Fighter 6 demo or
the VVL test --gtest_filter=NegativeSyncVal.CopyOptimalImageHazards.
Or by a simple Vulkan program that just tries to create a simple
multi-sampled 2D image with the alias flag set.
Reported-by: Spencer Fricke (@spencer-lunarg)
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/14926
Fixes: 11f8f333e23d ("anv: set a private binding when the image is not externally shared")
Reviewed-by: Nanley Chery <[email protected]>
Signed-off-by: Paulo Zanoni <[email protected]>
(cherry picked from commit 34b4e94f9f182337fa3754d01625dd7f917d400f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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fdd998fb by Sagar Ghuge at 2026-07-01T11:08:33+02:00
anv: Workaround game bug for Witcher3
Game does following:
1) BuildSizesKHR - Mode or flags are not set
2) BuildAccelerationStructuresKHR - Mode is set to Build
3) BuildAccelerationStructures - Mode is set to UPDATE
We need lookup maps in order to get the BVH update working otherwise, we
will hit the hang due to missing lookup map data.
Cc: mesa-stable
Signed-off-by: Sagar Ghuge <[email protected]>
Acked-by: Iván Briano <[email protected]>
(cherry picked from commit da325ef1d4c36dd29431ef7364b955fdea37c502)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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a6efeaa4 by Samuel Pitoiset at 2026-07-01T11:08:33+02:00
spirv: allow mapping readonly buffers with struct members
The Vulkan spec changed to allow this. If all members or the variable
are NonWriteable, it's treated as R, otherwise RW.
This fixes a new VKCTS test
dEQP-VK.binding_model.descriptor_heap.storage_buffer.non_writable.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit f108feb48ff9101dfb826b6515f00852c60d1eff)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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5cf4d37a by Samuel Pitoiset at 2026-07-01T11:08:33+02:00
radv: fix clearing the streamout state on GFX12
If the same cmdbuf is re-submitted, the zero clear must be done by
the GPU, otherwise this is causing GPU hangs.
This fixes new VKCTS coverage
dEQP-VK.transform_feedback.simple.simultaneous_command_buffers*
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 3f5bf3ffa2d9cd7a42c6caaa16d3bf613539c225)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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b000b5dc by Lionel Landwerlin at 2026-07-01T11:08:33+02:00
brw: add shader key to enable robust SLM accesses
Some games appear to rely on well defined behavior of OOB. If we start
vectorizing loads we can run into issues like with Hitman2 where a
compute shaders has 2 vec1 loads and the first load for first lane in
the workgroup is at a negative offset.
Signed-off-by: Lionel Landwerlin <[email protected]>
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <[email protected]>
(cherry picked from commit bbfa464544a8ff3674559c329d79b63744286c72)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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56a5ea74 by Lionel Landwerlin at 2026-07-01T11:08:33+02:00
anv: add hitman2 workaround for SLM load vectorization
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15140
Cc: mesa-stable
Reviewed-by: Paulo Zanoni <[email protected]>
(cherry picked from commit 3eb05675c7d621102178cd19f8ca9c0ddabc9af4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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039bed6d by Samuel Pitoiset at 2026-07-01T11:08:34+02:00
vulkan: fix initializing address flags
Fixes: b7bf4e53049 ("vulkan/runtime: build (address|copy)_flags for vk_buffer")
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 9063561b2d38857b8153de665fe60be8726fc6ca)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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3a040a4a by Christian Gmeiner at 2026-07-01T11:08:34+02:00
pan/va: Only widen constants on 32-bit instructions
va_lookup_constant(..) matches a 32-bit constant that is a zero or
sign extension of an 8/16-bit LUT entry and returns a single byte or
half of that entry with a widening swizzle. The hardware only extends
the selected sub-word on 32-bit instructions. On 8/16-bit vector
instructions the same swizzle replicates the sub-word to all lanes,
turning a constant like (0x3f80, 0x0000) into (0x3f80, 0x3f80).
Found by dEQP-VK.compute.pipeline.workgroup_memory_explicit_layout.
alias.f32_to_u16_array_* which compares an aliased u16vec2 view of
1.0f against (0x3f80, 0x0000) with ICMP_OR.v2u16.
Fixes: 9cfafbb09be ("pan/va: Try widening small constants")
Signed-off-by: Christian Gmeiner <[email protected]>
Reviewed-by: Lorenzo Rossi <[email protected]>
(cherry picked from commit 08ae961541e4f8bf94e1fc47718e7b21579c9cec)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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0e1efb3d by Arkady Shlykov at 2026-07-01T11:08:34+02:00
Add offset getter for image intrinsics
Treat 2nd source (four-coordinate vector) as an offset for image intrinsics
in nir_get_io_offset_src_number. Allow to handle image and non-image
intrinsics in the same consistent way.
Fixes: 7f7ba20cca ("brw: Implement divergent atomics fusion optimization (single message approach)")
Reviewed-by: Lionel Landwerlin <[email protected]>
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit b723e99a54b786d15486a480bb55d6401a4b5b4d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ec2b425b by Timothy Arceri at 2026-07-01T11:08:34+02:00
util/u_range_remap: allow insert to truncate range
Range remap is used to help validate overlapping explicit locations
during compilation and later to remap uniform locations. After
explicit locations have been validated arrays might have been
optimised to remove unused elements from the end, we need to
allow for this when updating the existing entries from the earlier
validation with their actual remap values.
Here we add a bool param allow_range_truncation to indicate when
we want to allow truncation vs only allowing exact matches.
Fixes: e05225406617 ("glsl: make use of u_range_remap for uniform remapping")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15593
Reviewed-by: Marek Olšák <[email protected]>
(cherry picked from commit 118260026361b8ac7d2f826a5e52487aef669f98)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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92e1e6a5 by Marc Alcala Prieto at 2026-07-01T11:08:34+02:00
panvk: Fix DRM format modifiers for multi-planar YUV formats
Return the right amount of planes depending on the format.
In our case:
- For linear modifiers, and as per the Vulkan specification (see below),
we must report the plane count of the format.
- For optimal, report the plane count depending on the format as well.
However, AFBC is not supported at the moment on multi-planar YUV
formats, and thus it will be filtered out later.
The spec says:
If an image is linear, then the partition is the same for memory planes
and for format planes. Therefore, if the returned drmFormatModifier is
DRM_FORMAT_MOD_LINEAR, then drmFormatModifierPlaneCount must equal the
format planecount, and drmFormatModifierTilingFeatures must be identical
to the VkFormatProperties2::formatProperties.linearTilingFeatures
returned in the same pNext chain.
Fixes: d970fe2e9d6 ("panfrost: Add a Vulkan driver for Midgard/Bifrost GPUs")
Reviewed-by: Boris Brezillon <[email protected]>
(cherry picked from commit 2ce9bc68585af69cd8e46d38139f82b0efdc4ecc)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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e597c318 by Lionel Landwerlin at 2026-07-01T11:08:34+02:00
vulkan: condition cmd_queue initialization to driver need
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 6dce207497 ("vulkan/cmd_queue: Use a linear allocator")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15587
Reviewed-by: Konstantin Seurer <[email protected]>
(cherry picked from commit ce6647daa543690eff8a72c080eee118fb1a63bf)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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c6f25c55 by Samuel Pitoiset at 2026-07-01T11:08:34+02:00
radv/amdgpu: fix computing allocated VRAM for imported BOs from fd
It's possible to know if the BO is CPU-acessible or not and adjust the
correct heap value.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15725
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 97618eee3d4a8160790cba2f2353c593738a1a06)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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7eeb36e4 by Mike Blumenkrantz at 2026-07-01T11:08:34+02:00
vulkan: update spec to 1.4.350
(cherry picked from commit 7a56d8112f21a0c2abffbc374dc3b52ee209acdc)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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8235120f by Konstantin Seurer at 2026-07-01T11:08:34+02:00
vulkan: Fixes for a spec update
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 9d7bfb42fb69f8b3cbe130f9350a234c38ad2487)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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a5ff12a2 by Konstantin Seurer at 2026-07-01T11:08:34+02:00
vulkan,spirv: Update spec to 1.4.352
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit cfdaa26a646569ca39e97ee99f1a0159a76c0292)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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a9fcecf8 by Samuel Pitoiset at 2026-07-01T11:08:34+02:00
vulkan: Update spec to 1.4.353
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 0ec4cc9cd5a09831b2447a342b44fcd05ae362f2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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f5a611bb by Icenowy Zheng at 2026-07-01T11:08:34+02:00
vulkan: update spec to 1.4.354
Signed-off-by: Icenowy Zheng <[email protected]>
Acked-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 8d17c7e282a7b292534931d6ea0063e4223a8c4b)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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95868851 by Mike Blumenkrantz at 2026-07-01T11:08:34+02:00
zink: set NO_TASK_SHADER for pipeline layouts with shader objects
cc: mesa-stable
(cherry picked from commit d3cae5ab71f62e7234c8bbedb4ba243df7de669d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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3fea8cbc by Benjamin Cheng at 2026-07-01T11:08:34+02:00
mesa/st: use col0 attrib from provoking vertex for feedback
When clipping triangles and flatshade is enabled, the clip stage does
not copy the col0 attribute to the new vertices. GL_FEEDBACK does not
expect flatshaded outputs, and thus uninitialized memory is returned to
the app.
Handle it in the st_cb_feedback by copying col0 from the provoking vertex.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15304
Signed-off-by: Benjamin Cheng <[email protected]>
Reviewed-by: Roland Scheidegger <[email protected]>
(cherry picked from commit 04b23a9251dcce9476c8db8be211aefae59c657a)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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62f74eb1 by Mike Blumenkrantz at 2026-07-01T11:08:35+02:00
zink: always use src stages when flushing glMemoryBarrier calls
this otherwise fails to sync e.g., compute -> vertex input
cc: mesa-stable
(cherry picked from commit 80f2aeb41726b61541fb40bed8b3f14e2358950f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ff474adf by Mike Blumenkrantz at 2026-07-01T11:08:35+02:00
zink: always flush specified memory access for glMemoryBarrier calls
it was probably fine before, but this needs to be more broad for future work
cc: mesa-stable
(cherry picked from commit c4cb6fdb5afeab8cbe76d9aa0db73ee4aae7a48c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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168e3e52 by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: Fix stale end-comment on __glXInitialize direct-rendering block
The closing comment claimed the block was guarded by
GLX_DIRECT_RENDERING && !GLX_USE_APPLEGL, but the matching #if was widened to
also enable the block when GLX_USE_APPLE is defined.
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 12698f53c35153cd4198a79c9141f8a45b4a4bb8)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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77b97a06 by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: drop redundant __glXErrorString forward declaration
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 0001305b547fe2cab206a4441cd9250f3007d08f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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e0687e37 by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: fix DRI3-not-available diagnostic skip on macOS
568a4ca8997 ("glx: ignore zink check for has_explicit_modifiers and DRI3 on MacOS.") wrapped the
DRI3-not-available diagnostic in #if !defined(GLX_USE_APPLE), but the macro that indicates "this
is the macOS DRI platform" is GLX_USE_APPLEGL, not GLX_USE_APPLE.
Fixes: 568a4ca899762fe96fc9b34d2288d07e6656af87
CC: [email protected]
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit dfb789a0949ec6db7d0b31ad69586d31b8c36b35)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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c89ecd9f by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: NULL-check frontend_screen in glXCreateContextAttribsARB
Some implementations (eg: AppleGL) never populate it.
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 025d851013b008846304077ee483da85768c030c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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b195a821 by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: simplify FBConfig wire decode
The AppleGL arm in the FBConfig property parser duplicated the non-AppleGL count subtraction and twice forced
drawableType to (GLX_WINDOW_BIT | GLX_PIXMAP_BIT | GLX_PBUFFER_BIT) to paper over what XQuartz might report; a
separate #ifndef hid the SGIX optimal-pbuffer and visual-select-group cases from the AppleGL build even though
XQuartz never sends those tags. Drop both drawableType force-ORs so the field reflects exactly what the server
reports, collapse the byte-identical count fork, and let the SGIX cases compile unconditionally.
This is the one commit in this series with a visible runtime change: under AppleGL an FBConfig's
drawableType now matches the server's reply rather than a forced superset, so applications may see fewer drawable
types than they used to if XQuartz under-reports. That is the desired direction; if it breaks something, the fix
belongs in XQuartz, not in libGL.
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit d360c0895ca7738b20680b31b8697e46436f0bc4)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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7d5465d4 by Connor Abbott at 2026-07-01T11:08:35+02:00
nir/lower_amul: fix infinity recursion with different phi source order
Fixes: 5e08f070f0f ("nir: add nir_lower_amul pass")
Reviewed-by: Georg Lehmann <[email protected]>
(cherry picked from commit f83b152669bc1eb726156c1cdabba6321fe31d37)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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4da277dd by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: free glx_drawable on CreateDRIDrawable failure
CreateDrawable() and glXCreateGLXPixmap() insert glxDraw into priv->glXDrawHash via InitGLXDrawable
before attempting CreateDRIDrawable. On the CreateDRIDrawable failure path both call
protocolDestroyDrawable to release the X-server-side resource but never call DestroyGLXDrawable to
release the client-side glx_drawable, leaking it and leaving a dangling priv->glXDrawHash entry
that subsequent lookups against the xid (now reused by the server) would resolve to.
Fixes: 4833104718677caad0027d5e7539ca9bba389392
CC: mesa-stable
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 8d3724cab138b645711bfa791f817bbb1ee179ee)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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8f4086f8 by Samuel Pitoiset at 2026-07-01T11:08:35+02:00
radv: fix a memleak with embedded samplers and descriptor heap
Fixes a memory leak detected by ASAN with
dEQP-VK.binding_model.descriptor_heap.shader_object_invariance.shader_object_invariance.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 73aee40a51fe90027cf262ba5dca4384bb664577)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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ac58313c by Samuel Pitoiset at 2026-07-01T11:08:35+02:00
radv: disable VRS with MSAA 8x on GFX11-11.7 to prevent GPU hangs
DX12/Vulkan only require up to 4x anyways. It's also simpler to disable
all rates with MSAA 8x because the Vulkan spec requires to lower to
2x1 or 1x2 otherwise and it's not really possible with VRS attachments.
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 84f436436880e8d2748143078c09279a034006c5)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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3b82e986 by Samuel Pitoiset at 2026-07-01T11:08:35+02:00
radv: disable VRS for flat shading with MSAA 8X to prevent GPU hangs on GFX11
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/work_items/15081
Signed-off-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 298cdd04de11a78792edb58a75a5be8c755296a1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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7850fbc2 by QwertyChouskie at 2026-07-01T11:08:35+02:00
docs/features: Fix typo
Fixes: 2088f359 ("docs/features: Update extensions for softpipe")
(cherry picked from commit 2990ae089c55d14e5f09c8855b419bb6bb5cc043)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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c80c4d85 by Martin Roukala (né Peres) at 2026-07-01T11:08:35+02:00
freedreno/ci: document more failures for the a750-gl-cl job
Thanks to Eric Engestrom for figuring out the commits that forgot to
document these issues.
Fixes: 73f0d8ed51d8 ("ci: add api@clgetmemobjectinfo to fails")
Fixes: 47bde74e9191 ("ci: update OpenCL 3.1 piglit fails")
(cherry picked from commit 8a571ad67cf58efd3c3ec592c1b7618822cc340c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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b18d8342 by Mike Blumenkrantz at 2026-07-01T11:08:35+02:00
zink: free nir if cs program create fails
cc: mesa-stable
(cherry picked from commit 22ebf384603eb451aab263097680be9a0995bb40)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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cda1bc19 by Jesse Natalie at 2026-07-01T11:08:35+02:00
util: Fix u_math on MSVC arm64
MSVC can't do inline asm, use intrinsics to get at FPCR.
Note that MSVC arm32 support is dead so just no-op the
inline asm for that arch.
Fixes: 44c03f8ba65 ("util, llvmpipe: flush subnormals to zero on ARM/AArch64")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15685
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/15677
(cherry picked from commit 7906510e0ec8480edfeecd9a8b4985e7e44abc2e)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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f45102a5 by Jianfeng Liu at 2026-07-01T11:08:35+02:00
freedreno/drm: Fix uninitialized read of BO metadata on import
msm_bo_get_metadata() used drmCommandWrite(), whose ioctl direction is
write-only, so the kernel's req->len (the actual stored metadata length)
is never copied back to userspace. Worse, the function returns success
even for BOs that were never given metadata via MSM_INFO_SET_METADATA --
in that case the kernel copies zero bytes but leaves the caller's struct
untouched.
Callers (the a6xx dmabuf import path and the GL_EXT_memory_object
dedicated-memory path) then trust the uninitialized fdl_metadata.modifier.
On a6xx/a7xx this garbage value falls through to the default (unsupported
modifier) branch of fd6_layout_resource_for_handle(), so importing
external dmabufs that carry no freedreno metadata fails with
EGL_BAD_ALLOC. Observed on Qualcomm platforms when Chromium imports
V4L2/iris video decode capture buffers, causing flicker/tear.
Fix it at the source in msm_bo_get_metadata():
* zero-initialize the caller's buffer so bytes the kernel doesn't fill
are zero (robust regardless of kernel version);
* use drmCommandWriteRead() so req->len is read back;
* return -ENODATA when the kernel stored no (or partial) metadata, so
callers fall back to their own layout defaults -- restoring the
pre-metadata behavior for metadata-less BOs (dmabuf -> LINEAR,
dedicated memobj -> the existing a6xx UBWC default).
Cc: mesa-stable
Fixes: 68c53ec2c2b ("freedreno: Add layout metadata support")
Signed-off-by: Jianfeng Liu <[email protected]>
(cherry picked from commit e9115e448f7bf1ee36d162be36b009f031e9821d)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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59207303 by Lionel Landwerlin at 2026-07-01T11:08:35+02:00
anv/brw: fixup 64bit array image accesses
We forgot to handle sliced view of an arrayed image.
The base address of the HW descriptor not changing we need to read the
base array index and add it to the Z coordinate to compute the right
texel location.
Signed-off-by: Lionel Landwerlin <[email protected]>
Fixes: 723e52cbcc ("anv: Support putting image base address and image params in surface state")
Reviewed-by: Ivan Briano <[email protected]>
(cherry picked from commit be89a173d5000483ba08ef42f8a544b0789bc011)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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20863b7b by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
zink: fix GLX_USE_APPLE typo (should be GLX_USE_APPLEGL)
The intent of these guards is "skip on the AppleGL/XQuartz DRI platform"; the macro for that is
GLX_USE_APPLEGL, not GLX_USE_APPLE.
Fixes: 899fcaf2374 ("zink: Avoid issues when kopper tries using XCB WSI on Apple.")
Fixes: 191d7c6cb61 ("kopper: Add '#if' guard around `loader_dri3_get_pixmap_buffer` to stop missing symbol on MacOS.")
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 6a943a2660b0b4214fff0f1f7164b2f9bf569d0f)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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06c7b21f by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx/apple: free gc in applegl_destroy_context
applegl_destroy_context only released the apple_glx_context backing store and left the
struct glx_context allocation behind, leaking on every glXDestroyContext and on the
apple_glx_create_context failure paths in applegl_create_context_attribs (which calls
gc->vtable->destroy(gc) and then returns NULL). Add the free(gc) so applegl matches
every other backend's destroy slot (dri_destroy_context, indirect_destroy_context),
making gc->vtable->destroy(gc) a complete teardown on its own.
Fixes: 6849916170c0 ("glx: Split indirect and applegl implementations into different files")
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit 795f6a3b80aebe61ea9baa9d8000be72af8ea1fe)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
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efb804aa by JaeHoon Lee at 2026-07-01T11:08:35+02:00
v3dv: only report 16-bit float formats as blendable at 32/64 bpp
The V3D_INTERNAL_TYPE_16F case of format_supports_blending() returned
bpp == V3D_INTERNAL_BPP_32 || V3D_INTERNAL_BPP_64;
The second operand is a bare enum constant (V3D_INTERNAL_BPP_64 != 0),
so the expression is always true and every 16-bit float format is
reported as blendable regardless of its bit depth, contradicting the
comment just above it (hardware blending is only supported for 4x8
unorm, 2x16-bit float or 4x16-bit float render targets). Compare bpp
against the constant, like the first operand already does.
Fixes: ebbd32647289 ("v3dv: only expose blending on formats that support it")
(cherry picked from commit 87ba38379e235013dbcdff04204f95ba3c9ba8fc)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
48d5557e by JaeHoon Lee at 2026-07-01T11:08:35+02:00
vc4: fix last_layer selection in the blit sampler view
vc4_blit() built the sampler-view template with
.last_layer = (PIPE_TEXTURE_2D ? depth - 1 : array_size - 1)
where the ternary condition is a bare enum constant (PIPE_TEXTURE_2D),
so it is always true and last_layer is always taken from the 3D depth
slice count instead of the array size. Test the actual resource
target, matching the equivalent code in v3d_blit(): the depth slice
count only applies to 3D textures.
Fixes: ceb923bc2a13 ("vc4: add specific stencil blit path")
(cherry picked from commit df8b16ed2f0568909b8457e14a0ab777ce1c758c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
538cb7cc by Alessandro Astone at 2026-07-01T11:08:35+02:00
anv: Support VK_ANDROID_native_buffer older than version 11
The `ahb` field in VkNativeBufferANDROID was added in spec version 11.
We don't actually need to use it, since we can get the same info from the
gralloc handle instead.
There is just one minor inconvenience: our vk_android_get_anb_layout helper
takes a VkImageCreateInfo and not a VkNativeBufferANDROID directly; so here we
simply assert that VkImageCreateInfo did in fact contain VkNativeBufferANDROID
Fixes: 0c523b66619 ("anv: Use gralloc helper to get tiling")
Reviewed-by: Jianxun Zhang <[email protected]>
Reviewed-by: Juston Li <[email protected]>
(cherry picked from commit 0eeb51a58d9abf5d48212b6b7ffe01d9085bffbd)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
68f77f91 by Jeremy Huddleston at 2026-07-01T11:08:35+02:00
glx: fix per-display drawHash / zombieGLXDrawable / dri2Hash leak on GLX_USE_APPLE builds
__glXInitialize allocates dpyPriv->drawHash, dpyPriv->zombieGLXDrawable and (later) dpyPriv->dri2Hash
under defined(GLX_DIRECT_RENDERING) && (!defined(GLX_USE_APPLEGL) || defined(GLX_USE_APPLE)), but
the matching cleanup in glx_display_free, free_zombie_glx_drawable and the init_fail path is only
gated on defined(GLX_DIRECT_RENDERING) && !defined(GLX_USE_APPLEGL). On a GLX_USE_APPLE build the
allocations fire but the cleanup does not, leaking the table on every Display close (and on every
init_fail path). Widen the cleanup-side guards to match the allocation side.
Fixes: 97b6851815a ("apple: Extended Apple feature support using GLX_USE_APPLE.")
Signed-off-by: Jeremy Huddleston Sequoia <[email protected]>
(cherry picked from commit fa8fa25d6077eac3d0206495b5ecb1ddc5066a1c)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
aadcd273 by Valentine Burley at 2026-07-01T11:08:35+02:00
zink/ci: Remove zink-anv-cml-asan job
The CML runners are getting retired in the Collabora lab.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit eac18963b0ecaa82b5e02335bf556369a1442733)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
88379bd0 by Valentine Burley at 2026-07-01T11:08:35+02:00
intel/ci: Remove nightly CML jobs, retire runner
The CML runners are getting retired in the Collabora lab.
Cc: mesa-stable
Signed-off-by: Valentine Burley <[email protected]>
(cherry picked from commit fd16393e56ac4b3fe213048f45e4f2477cbb43c1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
053b820c by Mike Blumenkrantz at 2026-07-01T11:08:35+02:00
st/pbo_compute: account for drivers failing to create cs shaders
this can happen if memory allocations fail
cc: mesa-stable
(cherry picked from commit 8cf9a06e154dec3854d3bdc1d050769e3d560423)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
aa4a8966 by Yiwei Zhang at 2026-07-01T11:08:36+02:00
vulkan/android: force linear for mutable format
We need a better gralloc private query to forward the mutable bit along
with the format list for a private vendor usage bit, and leave the
decision to gralloc. For now, resolve mutable bit to CPU_WRITE_RARELY to
implicitly force LINEAR.
Cc: mesa-stable
Reviewed-by: Valentine Burley <[email protected]>
Reviewed-by: Roman Stratiienko <[email protected]>
(cherry picked from commit d02b25157c68804c4e6da613faf0f38a3bcca6d3)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
a50a8daa by Yiwei Zhang at 2026-07-01T11:08:36+02:00
venus/wsi: skip VkPresentRegionsKHR when pRegions is NULL
The spec allows pRegions to be NULL while requiring swapchainCount to
match the swapchains being presented to. So we should avoid copying from
NULL, and it's simpler to skip VkPresentRegionsKHR entirely.
Fixes: f216c109be4 ("venus: add a deep copy helper for VkPresentInfoKHR")
(cherry picked from commit 1dbb4d0df57507ccaf994a49f60f28d772250517)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
de25e348 by ljohnson at 2026-07-01T11:08:36+02:00
venus/wsi: deep copy pRectangles when cloning presentation info
v2 (zzyiwei): minor refactors
Fixes: f216c109be4 ("venus: add a deep copy helper for VkPresentInfoKHR")
(cherry picked from commit 311a437c75a449bd8acf786f97d8856a8788cd56)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/42587>
- - - - -
2e9f4f2d by Eric Engestrom at 2026-07-01T16:16:13+02:00
docs: add release notes for 26.1.4
- - - - -
6dfbc555 by Eric Engestrom at 2026-07-01T16:16:13+02:00
VERSION: bump for 26.1.4
- - - - -
3ebd859c by Timo Aaltonen at 2026-07-02T09:13:53+03:00
Merge branch 'upstream-unstable' into debian-unstable
- - - - -
450015ec by Timo Aaltonen at 2026-07-02T09:14:25+03:00
version bump
- - - - -
0fa864a1 by Timo Aaltonen at 2026-07-02T10:09:28+03:00
rules: Enable freedreno on x86 too, for FEX.
- - - - -
250 changed files:
- .pick_status.json
- VERSION
- bin/gen_release_notes.py
- bin/gen_release_notes_test.py
- bin/install_megadrivers.py
- bin/people.csv
- debian/changelog
- debian/rules
- docs/features.txt
- docs/relnotes.rst
- docs/relnotes/26.1.0.rst
- docs/relnotes/26.1.1.rst
- docs/relnotes/26.1.2.rst
- + docs/relnotes/26.1.3.rst
- + docs/relnotes/26.1.4.rst
- include/pci_ids/iris_pci_ids.h
- include/vulkan/vulkan_core.h
- + include/vulkan/vulkan_ubm.h
- meson.build
- src/amd/common/ac_gpu_info.c
- src/amd/common/ac_gpu_info.h
- src/amd/compiler/aco_assembler.cpp
- src/amd/compiler/aco_register_allocation.cpp
- src/amd/compiler/aco_scheduler_ilp.cpp
- src/amd/vulkan/bvh/update_gfx12.comp
- src/amd/vulkan/nir/radv_meta_nir.c
- src/amd/vulkan/nir/radv_nir_rt_common.c
- src/amd/vulkan/nir/radv_nir_rt_stage_monolithic.c
- src/amd/vulkan/nir/radv_nir_rt_traversal_shader.c
- src/amd/vulkan/radv_buffer.c
- src/amd/vulkan/radv_cmd_buffer.c
- src/amd/vulkan/radv_cmd_buffer.h
- src/amd/vulkan/radv_physical_device.c
- src/amd/vulkan/radv_pipeline_cache.c
- src/amd/vulkan/radv_pipeline_rt.c
- src/amd/vulkan/radv_queue.c
- src/amd/vulkan/radv_shader.c
- src/amd/vulkan/radv_shader_info.c
- src/amd/vulkan/radv_video.c
- src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c
- src/asahi/vulkan/hk_cmd_buffer.c
- src/broadcom/ci/broadcom-rpi5-fails.txt
- src/broadcom/ci/gitlab-ci.yml
- src/broadcom/compiler/vir_live_variables.c
- src/broadcom/vulkan/v3dv_cmd_buffer.c
- src/broadcom/vulkan/v3dvx_formats.c
- src/compiler/clc/clc_helpers.cpp
- src/compiler/glsl/gl_nir_link_uniforms.c
- src/compiler/glsl/gl_nir_linker.c
- src/compiler/glsl/serialize.cpp
- src/compiler/nir/nir_builtin_builder.c
- src/compiler/nir/nir_loop_analyze.c
- src/compiler/nir/nir_lower_amul.c
- src/compiler/nir/nir_lower_helper_writes.c
- src/compiler/nir/nir_lower_io.c
- src/compiler/nir/nir_opt_phi_precision.c
- src/compiler/nir/nir_opt_vectorize.c
- src/compiler/nir/nir_print.c
- src/compiler/nir/nir_range_analysis.c
- src/compiler/nir/tests/loop_analyze_tests.cpp
- src/compiler/spirv/NonSemanticShaderDebugInfo100.h
- src/compiler/spirv/spirv.core.grammar.json
- src/compiler/spirv/spirv.h
- src/compiler/spirv/vtn_opencl.c
- src/compiler/spirv/vtn_variables.c
- src/egl/drivers/dri2/platform_drm.c
- src/egl/drivers/dri2/platform_x11.c
- src/freedreno/ci/deqp-freedreno-a750-vk.toml
- src/freedreno/ci/freedreno-a306-fails.txt
- src/freedreno/ci/freedreno-a750-fails.txt
- src/freedreno/drm/msm/msm_bo.c
- src/freedreno/fdl/freedreno_lrz_layout.h
- src/freedreno/ir3/ir3_nir_opt_preamble.c
- src/freedreno/ir3/ir3_shader.h
- src/freedreno/vulkan/tu_cmd_buffer.cc
- src/freedreno/vulkan/tu_device.cc
- src/freedreno/vulkan/tu_device.h
- src/freedreno/vulkan/tu_pass.cc
- src/freedreno/vulkan/tu_queue.cc
- + src/gallium/auxiliary/draw/draw_nir.h
- + src/gallium/auxiliary/draw/draw_nir_lower_opcodes.py
- src/gallium/auxiliary/gallivm/lp_bld_arit.c
- src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
- src/gallium/auxiliary/meson.build
- src/gallium/auxiliary/vl/vl_compositor.c
- src/gallium/auxiliary/vl/vl_compositor_cs.c
- src/gallium/drivers/ethosu/mlw_codec/meson.build
- src/gallium/drivers/etnaviv/etnaviv_blend.c
- src/gallium/drivers/etnaviv/etnaviv_blt.c
- src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
- src/gallium/drivers/etnaviv/etnaviv_compiler.h
- src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
- src/gallium/drivers/etnaviv/etnaviv_context.c
- src/gallium/drivers/etnaviv/etnaviv_context.h
- src/gallium/drivers/etnaviv/etnaviv_format.c
- src/gallium/drivers/etnaviv/etnaviv_format.h
- src/gallium/drivers/etnaviv/etnaviv_internal.h
- src/gallium/drivers/etnaviv/etnaviv_nir.h
- + src/gallium/drivers/etnaviv/etnaviv_nir_lower_128bit.c
- src/gallium/drivers/etnaviv/etnaviv_resource.h
- src/gallium/drivers/etnaviv/etnaviv_rs.c
- src/gallium/drivers/etnaviv/etnaviv_screen.c
- src/gallium/drivers/etnaviv/etnaviv_shader.h
- src/gallium/drivers/etnaviv/etnaviv_state.c
- src/gallium/drivers/etnaviv/etnaviv_texture.c
- src/gallium/drivers/etnaviv/etnaviv_texture_desc.c
- src/gallium/drivers/etnaviv/etnaviv_texture_state.c
- src/gallium/drivers/etnaviv/etnaviv_transfer.c
- src/gallium/drivers/etnaviv/meson.build
- src/gallium/drivers/iris/iris_program.c
- src/gallium/drivers/iris/iris_screen.c
- src/gallium/drivers/llvmpipe/lp_screen.h
- src/gallium/drivers/llvmpipe/lp_state_cs.c
- src/gallium/drivers/llvmpipe/lp_test_arit.c
- src/gallium/drivers/panfrost/pan_jm.c
- src/gallium/drivers/radeonsi/si_sdma_copy_image.c
- src/gallium/drivers/radeonsi/si_shader_info.c
- src/gallium/drivers/radeonsi/si_video_dec.c
- src/gallium/drivers/radeonsi/si_vpe.c
- src/gallium/drivers/v3d/v3d_blit.c
- src/gallium/drivers/v3d/v3d_context.c
- src/gallium/drivers/v3d/v3d_context.h
- src/gallium/drivers/vc4/vc4_blit.c
- src/gallium/drivers/vc4/vc4_context.h
- src/gallium/drivers/vc4/vc4_draw.c
- src/gallium/drivers/vc4/vc4_state.c
- src/gallium/drivers/virgl/virgl_context.c
- src/gallium/drivers/zink/ci/gitlab-ci.yml
- src/gallium/drivers/zink/ci/traces-zink.yml
- src/gallium/drivers/zink/ci/zink-anv-adl-fails.txt
- − src/gallium/drivers/zink/ci/zink-anv-cml-fails.txt
- − src/gallium/drivers/zink/ci/zink-anv-cml-flakes.txt
- − src/gallium/drivers/zink/ci/zink-anv-cml-skips.txt
- − src/gallium/drivers/zink/ci/zink-anv-cml-validation-settings.txt
- src/gallium/drivers/zink/ci/zink-anv-tgl-fails.txt
- src/gallium/drivers/zink/zink_blit.c
- src/gallium/drivers/zink/zink_clear.c
- src/gallium/drivers/zink/zink_context.c
- src/gallium/drivers/zink/zink_context.h
- src/gallium/drivers/zink/zink_descriptors.c
- src/gallium/drivers/zink/zink_draw.cpp
- src/gallium/drivers/zink/zink_kopper.c
- src/gallium/drivers/zink/zink_program.c
- src/gallium/drivers/zink/zink_resource.c
- src/gallium/frontends/dri/kopper.c
- src/gallium/frontends/lavapipe/lvp_cmd_buffer.c
- src/gallium/frontends/rusticl/core/context.rs
- src/gallium/frontends/rusticl/core/platform.rs
- src/gallium/frontends/rusticl/core/program.rs
- src/gallium/frontends/rusticl/mesa/util/queue.rs
- src/gallium/frontends/rusticl/meson.build
- src/gallium/frontends/va/postproc.c
- src/gallium/targets/dri/meson.build
- src/gallium/targets/dril/meson.build
- src/gfxstream/guest/platform/meson.build
- src/glx/applegl_glx.c
- src/glx/create_context.c
- src/glx/drisw_glx.c
- src/glx/glx_pbuffer.c
- src/glx/glxext.c
- src/glx/meson.build
- src/imagination/pco/pco_ra.c
- src/imagination/vulkan/pvr_arch_cmd_buffer.c
- src/imagination/vulkan/pvr_arch_mrt.c
- src/imagination/vulkan/pvr_mrt.h
- src/imagination/vulkan/pvr_usc.c
- src/intel/blorp/blorp_blit.c
- src/intel/blorp/blorp_brw.c
- src/intel/blorp/blorp_clear.c
- src/intel/blorp/blorp_elk.c
- src/intel/blorp/blorp_priv.h
- src/intel/ci/gitlab-ci-inc.yml
- src/intel/ci/gitlab-ci.yml
- − src/intel/ci/iris-cml-fails.txt
- − src/intel/ci/iris-cml-flakes.txt
- src/intel/ci/traces-iris.yml
- src/intel/compiler/brw/brw_compiler.h
- src/intel/compiler/brw/brw_lower_logical_sends.cpp
- src/intel/compiler/brw/brw_nir.c
- src/intel/compiler/brw/brw_nir_lower_texel_address.c
- src/intel/compiler/brw/brw_opt_combine_constants.cpp
- src/intel/compiler/elk/elk_fs_combine_constants.cpp
- src/intel/genxml/meson.build
- src/intel/isl/isl.h
- src/intel/vulkan/anv_android.c
- src/intel/vulkan/anv_blorp.c
- src/intel/vulkan/anv_device.c
- src/intel/vulkan/anv_formats.c
- src/intel/vulkan/anv_image.c
- src/intel/vulkan/anv_nir_apply_pipeline_layout.c
- src/intel/vulkan/anv_private.h
- src/intel/vulkan/anv_shader_compile.c
- src/intel/vulkan/genX_cmd_buffer.c
- src/intel/vulkan/genX_gfx_state.c
- src/intel/vulkan/xe/anv_batch_chain.c
- src/kosmickrisp/vulkan/kk_cmd_buffer.c
- src/mesa/main/texparam.c
- src/mesa/state_tracker/st_cb_bitmap.c
- src/mesa/state_tracker/st_cb_feedback.c
- src/mesa/state_tracker/st_pbo_compute.c
- src/mesa/state_tracker/st_program.c
- src/microsoft/vulkan/dzn_cmd_buffer.c
- src/nouveau/compiler/nak_nir_lower_non_uniform_ldcx.c
- src/nouveau/vulkan/nvk_cmd_draw.c
- src/nouveau/vulkan/nvk_shader.c
- src/nouveau/vulkan/nvkmd/nouveau/nvkmd_nouveau_ctx.c
- src/panfrost/ci/gitlab-ci-inc.yml
- src/panfrost/ci/gitlab-ci.yml
- src/panfrost/compiler/bifrost/bi_lower_spill.c
- src/panfrost/compiler/bifrost/bi_ra.c
- src/panfrost/compiler/bifrost/bifrost_compile.c
- src/panfrost/compiler/bifrost/valhall/test/test-lower-constants.cpp
- src/panfrost/compiler/bifrost/valhall/va_insert_flow.c
- src/panfrost/compiler/bifrost/valhall/va_lower_constants.c
- src/panfrost/vulkan/jm/panvk_vX_cmd_buffer.c
- src/panfrost/vulkan/panvk_image.c
- src/panfrost/vulkan/panvk_physical_device.c
- src/util/00-mesa-defaults.conf
- src/util/00-radv-defaults.conf
- src/util/driconf.h
- src/util/float8.c
- src/util/tests/float8_test.cpp
- src/util/u_cpu_detect.h
- src/util/u_math.c
- src/util/u_math.h
- src/util/u_range_remap.c
- src/util/u_range_remap.h
- src/virtio/ci/android-angle-venus-anv-fails.txt
- src/virtio/ci/android-angle-venus-anv-skips.txt
- src/virtio/ci/deqp-android-angle-venus-anv.toml
- src/virtio/ci/gitlab-ci.yml
- src/virtio/vulkan/vn_queue.c
- src/virtio/vulkan/vn_ring.c
- src/virtio/vulkan/vn_wsi.c
- src/vulkan/registry/vk.xml
- src/vulkan/runtime/vk_android.c
- src/vulkan/runtime/vk_buffer.c
- src/vulkan/runtime/vk_command_buffer.c
- src/vulkan/runtime/vk_command_buffer.h
- src/vulkan/runtime/vk_nir_lower_descriptor_heaps.c
- src/vulkan/util/gen_enum_to_str.py
- src/vulkan/util/vk_cmd_queue_gen.py
- src/vulkan/util/vk_physical_device_features_gen.py
- src/vulkan/util/vk_physical_device_properties_gen.py
- src/vulkan/util/vk_physical_device_spirv_caps_gen.py
- src/vulkan/wsi/wsi_common.c
- src/vulkan/wsi/wsi_common_display.c
- src/vulkan/wsi/wsi_common_x11.c
- src/x11/x11_display.c
- src/x11/x11_display.h
The diff was not included because it is too large.
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/06ef208be22f23e677f60f3df55ace2d88491b7b...0fa864a14d4ddd0a3e49dafa03638d46d3237588
--
View it on GitLab: https://salsa.debian.org/xorg-team/lib/mesa/-/compare/06ef208be22f23e677f60f3df55ace2d88491b7b...0fa864a14d4ddd0a3e49dafa03638d46d3237588
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