RE: [PATCH 0/2] PCI/ASPM: Allow quirks to avoid L0s and L1

> -----Original Message-----
> From: Bjorn Helgaas <[email protected]>
> Sent: 2025年11月7日 2:37
> To: [email protected]
> Cc: Christian Zigotzky <[email protected]>; Manivannan Sadhasivam
> <[email protected]>; mad skateman <[email protected]>; R . T .
> Dickinson <[email protected]>; Darren Stevens <[email protected]>;
> John Paul Adrian Glaubitz <[email protected]>; Lukas Wunner
> <[email protected]>; luigi burdo <[email protected]>; Al
> <[email protected]>; Roland <[email protected]>; Hongxing Zhu
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; Bjorn Helgaas <[email protected]>
> Subject: [PATCH 0/2] PCI/ASPM: Allow quirks to avoid L0s and L1
> 
> From: Bjorn Helgaas <[email protected]>
> 
> We enabled ASPM too aggressively in v6.18-rc1.  f3ac2ff14834 ("PCI/ASPM:
> Enable all ClockPM and ASPM states for devicetree platforms") enabled
> ASPM L0s, L1, and (if advertised) L1 PM Substates.
> 
> L1 PM Substates and Clock PM in particular are a problem because they
> depend on CLKREQ# and sometimes device-specific configuration, and none
> of this is discoverable in a generic way.
> 
> df5192d9bb0e ("PCI/ASPM: Enable only L0s and L1 for devicetree platforms")
> (v6.18-rc3) backed off and omitted Clock PM and L1 Substates.
> 
> L0s and L1 are generically discoverable, but some devices advertise them
> even though they don't work correctly.  This series is a way to avoid L0s and
> L1 in that case.
> 
> Bjorn Helgaas (2):
>   PCI/ASPM: Cache Link Capabilities so quirks can override them
>   PCI/ASPM: Avoid L0s and L1 on Freescale Root Ports

Tested-by: Richard Zhu <[email protected]>

Best Regards
Richard Zhu

> 
>  drivers/pci/pcie/aspm.c | 42 ++++++++++++++++++++---------------------
>  drivers/pci/probe.c     |  5 ++---
>  drivers/pci/quirks.c    | 12 ++++++++++++
>  include/linux/pci.h     |  1 +
>  4 files changed, 36 insertions(+), 24 deletions(-)
> 
> --
> 2.43.0