Re: Delay slot in PowerISA?

On 2026-01-14 04:26, Felix Lechner wrote:
> Hi,
> 
> When I searched for "powerpc64 delay slot" today, the SearchAssist
> bubble on DuckDuckGo called delay slots are a "feature" on PowerPC.  
> The
> full text is at the bottom of this message.
> 
> However, both references in the text state the opposite, namely:
> 
>    "Some RISCs like PowerPC and ARM do not have a delay slot" [1]
> 
> and
> 
>    "MC88000 [...] and SPARC are RISC architectures that each have a
>    single branch delay slot; PowerPC, ARM, Alpha, V850, and RISC-V do
>    not have any." [2]
> 
> Personally, I remain uncertain because sample code in a presentation
> from 2014 has 'nop' instructions after the 'bl' instructions. [3] Does
> the PowerPC architecture have delay slots, please?
> 
> Please copy me on your reply.  I do not subscribe to this list.  
> Thanks!
> 
> Kind regards,
> Felix
> 
> [1] https://www.pagetable.com/?p=313
> [2] https://en.wikipedia.org/wiki/Delay_slot
> [3] pp.30ff,
> https://llvm.org/devmtg/2014-04/PDFs/Talks/Euro-LLVM-2014-Weigand.pdf
> 
> * * *
> 
> A delay slot in PowerPC64 architecture refers to the instruction that
> follows a branch instruction, which is executed regardless of whether
> the branch is taken. This feature helps manage the pipeline in the CPU,
> allowing for more efficient instruction processing.
> 
> Overview of Delay Slots in PowerPC64
> 
> Delay slots are a feature in certain RISC architectures, including
> PowerPC, that help manage instruction execution during branching. They
> allow the CPU to continue executing instructions while waiting for the
> outcome of a branch decision.
> 
> Functionality of Delay Slots
> 
> Purpose
> 
>     Delay slots are used to fill the gap created by branch 
> instructions,
>     which can cause a pipeline stall.  The instruction immediately
>     following a branch instruction is executed regardless of whether 
> the
>     branch is taken.
> 
> Implementation
> 
>     In PowerPC architectures, delay slots can be optional. Programmers
>     can choose to fill these slots with useful instructions or leave
>     them as no-operations (NOPs).  The behavior of delay slots can vary
>     based on the specific PowerPC implementation.
> 
> Examples of Delay Slot Usage
> 
> Independent Instructions
> 
>     If the instruction in the delay slot does not depend on the branch,
>     it can be executed without issues. For example, loading a value 
> from
>     memory that is not affected by the branch condition.
> 
> Dependent Instructions
> 
>     If the instruction modifies a register that the branch depends on,
>     it can lead to undefined behavior. For instance, if a branch
>     instruction relies on a register that is altered in the delay slot,
>     the outcome may not be as expected.
> 
> Conclusion
> 
> Delay slots in PowerPC64 are a mechanism to optimize instruction flow
> during branching. They can be filled with useful instructions or left 
> as
> NOPs, depending on the programmer's needs and the specific
> architecture's capabilities. Understanding how to effectively use delay
> slots can enhance performance in PowerPC applications.
> 
> Sources:
> 
>    https://www.pagetable.com/?p=313
>    https://en.wikipedia.org/wiki/Delay_slot


Hello Felix,

I will review the shared resources and also check with the relevant 
internal teams to confirm this. Since there seems to be some conflicting 
information from external sources, I want to make sure we have an 
accurate and well-referenced answer.

I will get back to you once I have confirmation.

Thanks,
Trupti